scholarly journals An in situ digital background calibration algorithm for multi-channel R-βR ladder DACs

2022 ◽  
pp. 100150
Author(s):  
Liang-Jian Lyu ◽  
Qingzhen Wang ◽  
Zepeng Huang ◽  
Xing Wu
Keyword(s):  
Background Calibration ◽  
Digital Background Calibration ◽  
Calibration Algorithm

A digital background calibration algorithm of a pipeline ADC based on output code calculation

2012 ◽  
Vol 33 (11) ◽  
pp. 115010
Author(s):  
Jianjian Shao ◽  
Weitao Li ◽  
Cao Sun ◽  
Fule Li ◽  
Chun Zhang ◽  
...  
Keyword(s):  
Background Calibration ◽  
Pipeline Adc ◽  
Digital Background Calibration ◽  
Output Code ◽  
Calibration Algorithm

scholarly journals A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

VLSI Design ◽  
2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Hongmei Chen ◽  
Yongsheng Yin ◽  
Honghui Deng ◽  
Fujiang Lin
Keyword(s):  
Average Energy ◽  
Low Complexity ◽  
Background Calibration ◽  
Calibration Technique ◽  
Farrow Structure ◽  
Digital Background Calibration ◽  
Sinusoidal Input ◽  
Calibration Algorithm ◽  
Fractional Delay Filter ◽  
Time Interleaved

A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources.

Digital Background-Calibration Algorithm for “Split ADC” Architecture

2009 ◽  
Vol 56 (2) ◽  
pp. 294-306 ◽  
Author(s):  
J.A. McNeill ◽  
M.C.W. Coln ◽  
D.R. Brown ◽  
B.J. Larivee
Keyword(s):  
Background Calibration ◽  
Digital Background Calibration ◽  
Calibration Algorithm

scholarly journals Low Power SAR ADC Design with Digital Background Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (11) ◽  
pp. 1757
Author(s):  
Shouping Li ◽  
Jianjun Chen ◽  
Bin Liang ◽  
Yang Guo
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Background Calibration ◽  
Digital Background Calibration ◽  
Common Mode Voltage ◽  
Capacitor Mismatch ◽  
Calibration Algorithm

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

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