A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-μm CMOS technology

2011 ◽  
Vol 42 (1) ◽  
pp. 113-126 ◽  
Author(s):  
Jun-Da Chen
2014 ◽  
Vol 24 (01) ◽  
pp. 1550002 ◽  
Author(s):  
Mina Amiri ◽  
Adib Abrishamifar

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.


2009 ◽  
Vol 64 (3) ◽  
pp. 233-240 ◽  
Author(s):  
Oliver Schmitz ◽  
Sven Karsten Hampel ◽  
Christian Orlob ◽  
Marc Tiebout ◽  
Ilona Rolfes

2017 ◽  
Vol 27 (03) ◽  
pp. 1850047
Author(s):  
Xin Zhang ◽  
Chunhua Wang ◽  
Yichuang Sun ◽  
Haijun Peng

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.


2014 ◽  
Vol 23 (05) ◽  
pp. 1450060 ◽  
Author(s):  
LEONARDO PANTOLI ◽  
VINCENZO STORNELLI

In this paper, we present, at transistor level, a very low complexity Gaussian monocycle pulse generator/modulator for DPSK low voltage and low power tunable ultra-wideband (UWB) applications. The pulse generator, simulated in a SMIC 0.13 μm CMOS technology, provides a tunable, both in pulse width duration and repetition time, Gaussian monocycle compliant with the sub-GHz ETSI band and suitable to be used in UWB radio applications. The preliminary IC simulation results show a pulse duration from 1 ns up to 20 ns with good pulse symmetry and with the DPSK modulation capability. The circuit power consumption is about 1 mW from a 1.8 V power supply.


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