Optimized buffer protection for network-on-chip based on Error Correction Code

Microelectronics Journal ◽

10.1016/j.mejo.2020.104799 ◽

2020 ◽

Vol 100 ◽

pp. 104799

Author(s):

Alan Pinheiro ◽

Daniel Tavares ◽

Felipe Silva ◽

Jarbas Silveira ◽

César Marcon

Keyword(s):

Error Correction ◽

Network On Chip ◽

Error Correction Code ◽

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A Method to Detect and Avoid Hardware Trojan for Network-on-Chip Architecture based on Error Correction Code and Junction Router (ECCJR)

International Journal of Advanced Computer Science and Applications ◽

10.14569/ijacsa.2020.0110476 ◽

2020 ◽

Vol 11 (4) ◽

Author(s):

Hafiz Ali Hamza Gondal ◽

Sajida Fayyaz ◽

Arooj Aftab ◽

Saira Nokhaiz ◽

Muhammad Bilal ◽

...

Keyword(s):

Error Correction ◽

Network On Chip ◽

Hardware Trojan ◽

Error Correction Code ◽

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Random and Triple burst error correction code with low redundancy for Network-on-Chip link

2018 International Conference on Computer Communication and Informatics (ICCCI) ◽

10.1109/iccci.2018.8441245 ◽

2018 ◽

Author(s):

M. Maheswari ◽

B. Murugeshwari

Keyword(s):

Error Correction ◽

Network On Chip ◽

Error Correction Code ◽

Burst Error ◽

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Power‐efficient error‐resilient network‐on‐chip router using selective error correction code scheme

Electronics Letters ◽

10.1049/el.2018.5389 ◽

2018 ◽

Vol 54 (24) ◽

pp. 1368-1370 ◽

Author(s):

C.‐L. Li ◽

Y.‐W. Kim ◽

Y.S. Lee ◽

T.H. Han

Keyword(s):

Error Correction ◽

Network On Chip ◽

Code Scheme ◽

Error Correction Code ◽

Error Resilient ◽

Power Efficient ◽

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Multi-bit Error Correction Technique for NTC based Network on Chip

AEBMS-2017, ICCET-2017, BBMPS-17, UPACEE-17, LHESS-17, TBFIS-2017, IC4E-2017, AMLIS-2017 & BEFM-2017 ◽

10.15242/heaig.e1217006 ◽

2018 ◽

Keyword(s):

Error Correction ◽

Network On Chip ◽

Correction Technique ◽

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Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects

2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184) ◽

10.1109/icoei48184.2020.9143002 ◽

2020 ◽

Author(s):

Kandala Anupama Satya Sai Lakshmi ◽

A.M Keerthi ◽

Kuruganti Madhu Sri ◽

M. Vinodhini

Keyword(s):

Error Correction ◽

Network On Chip ◽

On Chip ◽

Crosstalk Avoidance

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Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links

Microprocessors and Microsystems ◽

10.1016/j.micpro.2013.03.001 ◽

2013 ◽

Vol 37 (4-5) ◽

pp. 420-429 ◽

Author(s):

M. Maheswari ◽

G. Seetharaman

Keyword(s):

Error Correction ◽

Error Correction Code ◽

Burst Error ◽

On Chip ◽

Crosstalk Avoidance

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Quantum Error Correction Code Scheme used for Homomorphic Encryption like Quantum Computation

Jouranl of Information and Security ◽

10.33778/kcsa.2019.19.3.061 ◽

2019 ◽

Vol 19 (3) ◽

pp. 61-70

Author(s):

Il Kwon Sohn ◽

◽

Jonghyun Lee ◽

Wonhyuk Lee ◽

Woojin Seok ◽

...

Keyword(s):

Error Correction ◽

Quantum Computation ◽

Homomorphic Encryption ◽

Quantum Error Correction ◽

Code Scheme ◽

Error Correction Code ◽

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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

Oct. 17-19, 2017 Dubai (UAE) ◽

10.15242/dirpub.dir1017020 ◽

2018 ◽

Keyword(s):

Real Time ◽

Network On Chip ◽

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.5.1.3320 ◽

2014 ◽

Vol 5 (1) ◽

pp. 27-32

Author(s):

Jeeva Anusha ◽

◽

V. Thrimurthulu ◽

Keyword(s):

Vlsi Design ◽

Network On Chip ◽

Energy Modeling ◽

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