Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

2005 ◽  
Vol 45 (5-6) ◽  
pp. 790-793 ◽  
Author(s):  
Udo Schwalke ◽  
Yordan Stefanov
Keyword(s):  
Process Integration ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Nanometer Scale ◽  
High K

Process and Manufacturing Challenges for High-K Gate Stack Systems

1999 ◽  
Vol 567 ◽  
Author(s):  
M.C. Gilmer ◽  
T-Y Luo ◽  
H.R. Huff ◽  
M.D. Jackson ◽  
S. Kim ◽  
...  
Keyword(s):  
Silicon Surface ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Metal Electrode ◽  
Significant Variable ◽  
Tem Analysis ◽  
Physical Mechanisms ◽  
High K ◽  
Commercial Equipment

ABSTRACTA design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

2006 ◽  
Vol 9 (6) ◽  
pp. 1031-1036 ◽  
Author(s):  
Youhei Sugimoto ◽  
Hideto Adachi ◽  
Keisuke Yamamoto ◽  
Dong Wang ◽  
Hideharu Nakashima ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Plasma Oxidation ◽  
Post Deposition Annealing ◽  
High K ◽  
Post Deposition

Electrical characterization of high-k gate dielectrics on Ge with HfGeN and GeO2 interlayers

2010 ◽  
Vol 518 (9) ◽  
pp. 2505-2508
Author(s):  
Kana Hirayama ◽  
Wataru Kira ◽  
Keisuke Yoshino ◽  
Haigui Yang ◽  
Dong Wang ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
High K

Preparation and electrical characterization of amorphous BaO, SrO and Ba0.7Sr0.3O as high-k gate dielectrics

2010 ◽  
Vol 7 (2) ◽  
pp. 316-320 ◽  
Author(s):  
D. Müller-Sajak ◽  
A. Cosceev ◽  
C. Brand ◽  
K. R. Hofmann ◽  
H. Pfnür
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
High K
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