Bipolar magnetotransistor sensor with digital output

As color gamut of digital output device greatly affects image appearance, accurate and effective gamut description for output device is intensively required for developing high-quality image reproduction technique based on gamut mapping. In this paper, we present a novel method to determine color gamut of output device by using a specific 3D reconstruction technology and device ICC profile. First, we populate the device color space by uniform sampling in the RGB 3-Dimensional space, and convert these sampling points to CMYK color space. Then, we work out the CIE LAB value of these points according to the ICC profile of output device. At last, in CIE LAB color space the boundary of these points is determined by using a gamut boundary descriptor based on Ball-Pivoting Algorithm (BPA) proposed by Bernardini. Compared with the results generated by ICC3D, our proposed method can compute device gamut more efficiently and at the same time give a more accurate gamut description of the output device. It will be help to develop effective gamut mapping algorithms for color reproduction.

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Increase sensitivity of the sensor based on bipolar magnetotransistor by minimization initial output offset

2009 International Siberian Conference on Control and Communications ◽

10.1109/sibcon.2009.5044859 ◽

2009 ◽

Cited By ~ 2

Author(s):

R.D. Tikhonov ◽

A.V. Kozlov ◽

Yu.A. Chernova ◽

S.A. Polomoshnov

Keyword(s):

Bipolar Magnetotransistor

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An Extended-Counting Incremental Sigma–Delta ADC with Hardware-Reuse Technique

Journal of Circuits System and Computers ◽

10.1142/s0218126616500389 ◽

2016 ◽

Vol 25 (05) ◽

pp. 1650038

Author(s):

Xinji Zeng ◽

Jing Gao ◽

Liu Yang ◽

Jiangtao Xu

Keyword(s):

Conversion Rate ◽

Cmos Process ◽

Digital Output ◽

Sigma Delta ◽

Design And Implementation ◽

Conversion Time ◽

Cyclic Adc ◽

Sigma Delta Adc ◽

Oversampling Ratio ◽

Least Significant Bits

This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ/step.

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