Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
2010 ◽
Vol 56
(11)
◽
pp. 561-576
◽
2011 ◽
Vol 28
(1)
◽
pp. 1-14
◽
1997 ◽
Vol 102
(5)
◽
pp. 3199-3199
Keyword(s):
Keyword(s):
Keyword(s):
Keyword(s):
Keyword(s):