Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core

2011 ◽  
Author(s):  
J.C. Pena-Ramos ◽  
R. Parra-Michel
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Performance ◽  
Digital Signal ◽  
Network On Chip ◽  
On Chip

scholarly journals DSPSR: Digital Signal Processing Software for Pulsar Astronomy

2011 ◽  
Vol 28 (1) ◽  
pp. 1-14 ◽  
Author(s):  
W. van Straten ◽  
M. Bailes
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Graphics Processing Units ◽  
High Performance ◽  
Digital Signal ◽  
General Purpose ◽  
Design Decisions ◽  
Extensive Range ◽  
Processing Software ◽  
Graphics Processing

Abstractdspsr is a high-performance, open-source, object-oriented, digital signal processing software library and application suite for use in radio pulsar astronomy. Written primarily in C++, the library implements an extensive range of modular algorithms that can optionally exploit both multiple-core processors and general-purpose graphics processing units. After over a decade of research and development, dspsr is now stable and in widespread use in the community. This paper presents a detailed description of its functionality, justification of major design decisions, analysis of phase-coherent dispersion removal algorithms, and demonstration of performance on some contemporary microprocessor architectures.

System on Chip Design for Multi-Principle of Relay Protection in the FPGA

2014 ◽  
Vol 668-669 ◽  
pp. 857-861
Author(s):  
Peng Fei Hu ◽  
Yu Xiang Yuan ◽  
Zhi Juan Qu ◽  
Xue Ping Jiang
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Relay Protection ◽  
Digital Signal ◽  
System On Chip ◽  
Process Scheduling ◽  
Chip Design ◽  
Protection Devices ◽  
On Chip ◽  
Set Up

To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.

Design of Universal Signal Processing Machine Based on Multiple DSP

2013 ◽  
Vol 321-324 ◽  
pp. 1241-1244
Author(s):  
Yang Jian ◽  
Yu Hao Liu ◽  
Xi Jing Zhao ◽  
Hao Ming Chen
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Multiple Channel ◽  
Processing Machine ◽  
Large Memory ◽  
High Speed Data ◽  
Board Level

With the development and application of technique on high speed digital signal processing, wide bandwidth processing, high-speed data exchanging and flexible interlink structure have been the developing trend of modern high performance signal processing machine. In this paper, one universal signal processing machine is designed based on six pieces of ADSP-TS201 TigerSHARC processors, which owns good characteristics such as: large memory, excellent processing and data-exchanging performance, reconstitution, good expansibility. This signal processing machine adopts 64Bit, 66MHz CPCI bus standard and supports the function of extending processing performance by interlinking multiple boards. The high-speed data-exchanging is realized with multiple channel optical fiber. Furthermore, it owns board-level BIT function.

Sign in / Sign up

Export Citation Format

Share Document