Scope-aware data cache analysis for OpenMP programs on multi-core processors

2019 ◽  
Vol 98 ◽  
pp. 443-452 ◽  
Author(s):  
He Du ◽  
Wei Zhang ◽  
Nan Guan ◽  
Wang Yi
Keyword(s):  
Data Cache ◽  
Cache Analysis

scholarly journals Scope-Aware Data Cache Analysis for WCET Estimation

2011 ◽  
Author(s):  
Bach Khoa Huynh ◽  
Lei Ju ◽  
Abhik Roychoudhury
Keyword(s):  
Data Cache ◽  
Cache Analysis

Data Cache Analysis by Counting Integer Points

2021 ◽  
Author(s):  
Pascal Sotin ◽  
Quentin Vermande ◽  
Hugues Cassé
Keyword(s):  
Data Cache ◽  
Integer Points ◽  
Cache Analysis

Research of Web-OLAP system based on distributed data cache technology

2008 ◽  
Vol 28 (2) ◽  
pp. 515-518
Author(s):  
Li-juan CAO
Keyword(s):  
Data Cache ◽  
Distributed Data

scholarly journals Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache

2021 ◽  
Vol 18 (3) ◽  
pp. 1-22
Author(s):  
Michael Stokes ◽  
David Whalley ◽  
Soner Onder
Keyword(s):  
Energy Efficient ◽  
Data Access ◽  
Performance Degradation ◽  
Access Time ◽  
Data Cache ◽  
Energy Usage ◽  
Single Cycle ◽  
Performance Penalty

While data filter caches (DFCs) have been shown to be effective at reducing data access energy, they have not been adopted in processors due to the associated performance penalty caused by high DFC miss rates. In this article, we present a design that both decreases the DFC miss rate and completely eliminates the DFC performance penalty even for a level-one data cache (L1 DC) with a single cycle access time. First, we show that a DFC that lazily fills each word in a DFC line from an L1 DC only when the word is referenced is more energy-efficient than eagerly filling the entire DFC line. For a 512B DFC, we are able to eliminate loads of words into the DFC that are never referenced before being evicted, which occurred for about 75% of the words in 32B lines. Second, we demonstrate that a lazily word filled DFC line can effectively share and pack data words from multiple L1 DC lines to lower the DFC miss rate. For a 512B DFC, we completely avoid accessing the L1 DC for loads about 23% of the time and avoid a fully associative L1 DC access for loads 50% of the time, where the DFC only requires about 2.5% of the size of the L1 DC. Finally, we present a method that completely eliminates the DFC performance penalty by speculatively performing DFC tag checks early and only accessing DFC data when a hit is guaranteed. For a 512B DFC, we improve data access energy usage for the DTLB and L1 DC by 33% with no performance degradation.

Research on Data Cache Algorithm of Fog Computing Node

2020 ◽  
Author(s):  
Wenle Bai ◽  
Hongya Feng ◽  
Yuehai Wang ◽  
Xi Han
Keyword(s):  
Fog Computing ◽  
Data Cache ◽  
Computing Node

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

2004 ◽  
Author(s):  
Afrin Naz ◽  
Mehran Rezaei ◽  
Krishna Kavi ◽  
Philip Sweany
Keyword(s):  
Data Cache ◽  
Cache Performance

Design of an Intelligent Data Cache with Replacement Policy

2019 ◽  
Vol 10 (2) ◽  
pp. 87-107
Author(s):  
B. Shameedha Begum ◽  
N. Ramasubramanian
Keyword(s):  
Real Time ◽  
Replacement Policy ◽  
Data Cache ◽  
Cache Performance ◽  
Performance Requirements ◽  
Novel Approach ◽  
Reconfigurable Caches ◽  
Real Time Applications ◽  
Hard Real Time ◽  
Replacement Algorithms

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

scholarly journals An energy-efficient data cache with byte-repeat pattern encoding

2008 ◽  
Vol 5 (19) ◽  
pp. 833-839
Author(s):  
Seungmin Jung ◽  
Hyotaek Shim ◽  
Seungryoul Maeng
Keyword(s):  
Energy Efficient ◽  
Data Cache ◽  
Efficient Data ◽  
Pattern Encoding ◽  
Repeat Pattern

A versatile data cache for trace buffer support

2013 ◽  
Author(s):  
Chun-Hung Lai ◽  
Yun-Chung Yang ◽  
Ing-Jer Huang
Keyword(s):  
Data Cache

Circuit design of a dual-versioning L1 data cache

Integration ◽  
2012 ◽  
Vol 45 (3) ◽  
pp. 237-245 ◽  
Author(s):  
Azam Seyedi ◽  
Adrià Armejach ◽  
Adrián Cristal ◽  
Osman S. Unsal ◽  
Ibrahim Hur ◽  
...  
Keyword(s):  
Circuit Design ◽  
Data Cache ◽  
L1 Data
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