A statistical methodology for modeling and analysis of path delay faults in VLSI circuits

Computers & Electrical Engineering ◽

10.1016/s0045-7906(97)00017-7 ◽

1997 ◽

Vol 23 (5) ◽

pp. 319-328 ◽

Author(s):

Mustapha Hamad ◽

Sami Al-Arian ◽

David Landis

Keyword(s):

Vlsi Circuits ◽

Delay Faults ◽

Statistical Methodology ◽

Path Delay Faults ◽

Modeling And Analysis

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Modeling and analysis of path delay faults in VLSI circuits: a statistical approach

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 ◽

10.1109/icecs.2003.1301853 ◽

2004 ◽

Author(s):

M. Hamad

Keyword(s):

Statistical Approach ◽

Vlsi Circuits ◽

Delay Faults ◽

Path Delay Faults ◽

Modeling And Analysis

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A statistical model for path delay faults in VLSI circuits

Proceedings of SOUTHEASTCON '96 ◽

10.1109/secon.1996.510096 ◽

2002 ◽

Author(s):

M. Hamad ◽

D. Landis

Keyword(s):

Statistical Model ◽

Vlsi Circuits ◽

Delay Faults ◽

Path Delay Faults

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Parallel pattern fault simulation of path delay faults

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 ◽

10.1145/74382.74442 ◽

1989 ◽

Author(s):

M. Schulz ◽

F. Fink ◽

K. Fuchs

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Path Delay Faults ◽

Parallel Pattern

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults

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Functional-based ATPG for path delay faults

2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390) ◽

10.1109/ssmsd.2000.836465 ◽

2002 ◽

Author(s):

M. Michael ◽

S. Tragoudas

Keyword(s):

Delay Faults ◽

Path Delay Faults

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Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320072 ◽

2006 ◽

Author(s):

Shun-yen Lu ◽

Pei-ying Hsieh ◽

Jing-jia Liou

Keyword(s):

Critical Path ◽

Delay Faults ◽

Path Delay Faults ◽

Linear Structures ◽

Critical Path Delay

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Self-checking synchronous FSM network design for path delay faults

2017 IEEE East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2017.8110129 ◽

2017 ◽

Author(s):

S. Ostanin

Keyword(s):

Network Design ◽

Delay Faults ◽

Path Delay Faults

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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Deterministic broadside test generation for transition path delay faults

Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 ◽

10.1145/1785481.1785514 ◽

2010 ◽

Author(s):

Bo Yao ◽

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay Faults ◽

Transition Path

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