2006 IEEE/ACM International Conference on Computer Aided Design
Latest Publications

TOTAL DOCUMENTS

309

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

1595933891

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320061 ◽

2006 ◽

Cited By ~ 5

Author(s):

Shantanu Dutt ◽

Huan Ren ◽

Fenghua Yuan ◽

Vishal Suthar

Keyword(s):

Network Flow ◽

Incremental Placement

Designing Application-Specific Networks on Chips with Floorplan Information

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320058 ◽

2006 ◽

Cited By ~ 25

Author(s):

Srinivasan Murali ◽

Paolo Meloni ◽

Federico Angiolini ◽

David Atienza ◽

Salvatore Carta ◽

...

Keyword(s):

Networks On Chips ◽

Application Specific

Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320049 ◽

2006 ◽

Cited By ~ 3

Author(s):

Min Ni ◽

Seda Memik

Keyword(s):

Resource Allocation ◽

Power Optimization ◽

Leakage Power

Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320072 ◽

2006 ◽

Author(s):

Shun-yen Lu ◽

Pei-ying Hsieh ◽

Jing-jia Liou

Keyword(s):

Critical Path ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Linear Structures ◽

Critical Path Delay

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320137 ◽

2006 ◽

Cited By ~ 12

Author(s):

Mihir Choudhury ◽

Quming Zhou ◽

Kartik Mohanram

Keyword(s):

Design Optimization ◽

Single Event Upset ◽

Single Event

Guaranteeing Performance Yield in High-Level Synthesis

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320050 ◽

2006 ◽

Cited By ~ 14

Author(s):

W.-l. Hung ◽

Xiaoxia Wu ◽

Yuan Xie

Keyword(s):

High Level Synthesis ◽

High Level

A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320151 ◽

2006 ◽

Cited By ~ 3

Author(s):

Sean Shi ◽

Peng Yu ◽

David Pan

Keyword(s):

Simulation Model ◽

Circuit Simulation

Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320077 ◽

2006 ◽

Cited By ~ 1

Author(s):

Gordon Chiu ◽

Deshanand Singh ◽

Valavan Manohararajah ◽

Stephen Brown

Keyword(s):

Area Reduction ◽

Logic Functions ◽

Embedded Memories

Performance-Oriented Statistical Parameter Reduction of Parameterized Systems via Reduced Rank Regression

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320091 ◽

2006 ◽

Cited By ~ 5

Author(s):

Zhuo Feng ◽

Peng Li

Keyword(s):

Statistical Parameter ◽

Reduced Rank Regression ◽

Rank Regression ◽

Parameterized Systems ◽

Reduced Rank ◽

Parameter Reduction

System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320171 ◽

2006 ◽

Cited By ~ 1

Author(s):

Diana Marculescu ◽

Siddharth Garg

Keyword(s):

System Level ◽

Variability Analysis ◽

Voltage Frequency ◽

Level Process

2006 IEEE/ACM International Conference on Computer Aided DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs

Designing Application-Specific Networks on Chips with Floorplan Information

Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation

Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

Guaranteeing Performance Yield in High-Level Synthesis

A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power

Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs

Performance-Oriented Statistical Parameter Reduction of Parameterized Systems via Reduced Rank Regression

System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems

2006 IEEE/ACM International Conference on Computer Aided Design
Latest Publications