Auditory Distraction Compromises Random Generation

Author(s):  
John E. Marsh ◽  
Patrik Sörqvist ◽  
Niklas Halin ◽  
Anatole Nöstl ◽  
Dylan M. Jones

Auditory distraction of random generation – a quintessentially executive control task – was explored in three experiments. Random number generation was impaired by the mere presence of irrelevant auditory sequences that comprise digits, but not letters, and then only if the digits were heard in a canonical order (1, 2, 3 … or 3, 2, 1 …), not in random order (Experiments 1 and 2). Random letter generation was impaired by irrelevant letters heard in alphabetical order (a, b, c …) and reversed alphabetical order (i, h, g …), but not by numbers in canonical order or letters in random order (Experiment 3). Attempting to ignore canonical sequences – with items that are members of the same category as the to-be-generated items – reduced the randomness of the generated sequence, by decreasing the tendency to change the direction of the produced sequence for random number generation, and by increasing resampling of responses for random letter generation. Like other selective attention tasks, the cost of distraction to random generation appears to stem from preventing habitual responses assuming the control of action.

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Marc-André Schulz ◽  
Sebastian Baier ◽  
Benjamin Timmermann ◽  
Danilo Bzdok ◽  
Karsten Witt

AbstractIs the cognitive process of random number generation implemented via person-specific strategies corresponding to highly individual random generation behaviour? We examined random number sequences of 115 healthy participants and developed a method to quantify the similarity between two number sequences on the basis of Damerau and Levenshtein’s edit distance. “Same-author” and “different author” sequence pairs could be distinguished (96.5% AUC) based on 300 pseudo-random digits alone. We show that this phenomenon is driven by individual preference and inhibition of patterns and stays constant over a period of 1 week, forming a cognitive fingerprint.


2014 ◽  
Vol 1 ◽  
pp. 272-275 ◽  
Author(s):  
Vincent Canals ◽  
Antoni Morro ◽  
Josep L. Rosselló

2021 ◽  
Vol 485 ◽  
pp. 126736
Author(s):  
Muhammad Imran ◽  
Vito Sorianello ◽  
Francesco Fresi ◽  
Bushra Jalil ◽  
Marco Romagnoli ◽  
...  

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


2015 ◽  
Vol 137 ◽  
pp. 828-836 ◽  
Author(s):  
Che-Chi Shu ◽  
Vu Tran ◽  
Jeremy Binagia ◽  
Doraiswami Ramkrishna

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