scholarly journals FPGA‐based implementation of floating point processing element for the design of efficient FIR filters

2021 ◽  
Author(s):  
Tintu Mary John ◽  
Shanty Chacko
Keyword(s):  
Processing Element ◽  
Floating Point ◽  
Fir Filters

Design and implementation of a GaAs systolic floating-point processing element

1996 ◽  
Vol 143 (5) ◽  
pp. 325
Author(s):  
A. Beaumont-Smith ◽  
W. Marwood ◽  
C.C. Lim ◽  
K. Eshraghian
Keyword(s):  
Processing Element ◽  
Floating Point ◽  
Design And Implementation

A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing

2021 ◽  
pp. 1-14
Author(s):  
Wei Mao ◽  
Kai Li ◽  
Quan Cheng ◽  
Liuyao Dai ◽  
Boyu Li ◽  
...  
Keyword(s):  
Processing Element ◽  
Floating Point ◽  
Multiple Precision

scholarly journals Implementation of Parallel and Pipeline Scheme in the Standard Floating Point Adder to Improve the Speed

2019 ◽  
Vol 9 (2) ◽  
pp. 3073-3076
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Impulse Response ◽  
Floating Point ◽  
Infinite Impulse Response ◽  
Time Signal ◽  
Fir Filters ◽  
Iir Filters ◽  
In Series ◽  
Floating Point Numbers

In real time Signal Processing applications, the analogue signal is over sampled as per the Nyquist criterion in order to avoid the aliasing effect. Floating Point (FP) adder is used in the floating point Multiplier Accumulator Content (MAC) for real time Digital Signal Processing(DSP) applications. The heart of any real time DSP processor is floating point MAC. Floating Point MAC is constructed by Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters. FIR filters are stable than IIR filters because the impulse response is finite in FIR. Hence, for stable applications FIR filters are preferred. These FIR filters are intern constituted by FP adder, FP multiplier and shifter. In conventional floating point adder the two floating point numbers are added in series. Series means one after the other so the computation speed is less. In series fashion adding the floating point numbers means definitely it furnishes more delay[1] because in the addition of floating point numbers, along with the addition of mantissas; computation is required for both signs and exponents also. Hence, the processing speed is slow for computing the floating point numbers compared with fixed point numbers. Therefore, in order to increase the speed of operation for floating point addition in real time application i.e., to add 16- samples at a time which are in floating notation; a parallel and pipe line technique is going to be incorporated to the two bit floating point architecture. Before developing such novel architecture, a novel algorithm is developed and after, the novel architecture is developed. The total work is simulated by Modelsim 10.3c tool and synthesized by Xilinx 13.6 tool.

New floating point impedance simulation using operational amplifiers

1989 ◽  
Vol 136 (3) ◽  
pp. 155 ◽  
Author(s):  
T.S. Rathore ◽  
V. Singh
Keyword(s):  
Operational Amplifiers ◽  
Floating Point

Efficient implementation of Nth-band FIR filters based on a simple window method

1990 ◽  
Vol 137 (4) ◽  
pp. 302
Author(s):  
V. Anastassopoulos ◽  
T. Deliyannis
Keyword(s):  
Efficient Implementation ◽  
Fir Filters ◽  
Window Method
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