Modified artificial bee colony optimisation based FIR filter design with experimental validation using field‐programmable gate array

2016 ◽  
Vol 10 (8) ◽  
pp. 955-964 ◽  
Author(s):  
Atul Kumar Dwivedi ◽  
Subhojit Ghosh ◽  
Narendra D. Londhe
Keyword(s):  
Field Programmable Gate Array ◽  
Experimental Validation ◽  
Artificial Bee Colony ◽  
Filter Design ◽  
Fir Filter ◽  
Bee Colony ◽  
Field Programmable ◽  
Gate Array ◽  
Fir Filter Design

scholarly journals High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

2020 ◽  
Vol 9 (3) ◽  
pp. 764-770
Keyword(s):  
Decision Tree ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Decision Tree Algorithm ◽  
Tree Algorithm ◽  
Constant Multiplication ◽  
Field Programmable ◽  
Fir Filter Design ◽  
Complex Multiplier

In recent years, the filter is one of the key elements in signal processing applications to remove unwanted information. However, traditional FIR filters have been consumed more resources due to complex multiplier design. Mostly the complexity of the FIR filter is dominated by multiplier design. The conventional multipliers can be realized by Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) algorithms using shift and add/subtract operations. In this paper, a hybrid state decision tree algorithm is introduced to reduce hardware utilization (area) and increase speed in filter tap cells of FIR. The proposed scheme generates a decision tree to perform shift & addition and accumulation based on the combined SCM/MCM approach. The proposed FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) platform by using Verilog language. The experimental results of the DTG-FIR filter were averagely reduced the 48.259% of LUTs, 51.567 % of flip flops and 44.497 % of slices at 183.122 MHz of operating frequency on the Virtex-5 than existing VP-FIR.

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