Review on impact of nanoscale on CMOS circuits in VLSI design

2021 ◽  
Author(s):  
Gajula Lakshminarayana ◽  
S. Sribindu ◽  
L. Suneel ◽  
S. Gopala Krishna
Keyword(s):  
2016 ◽  
Vol 13 (10) ◽  
pp. 6999-7008
Author(s):  
N Anusha ◽  
T Sasilatha

Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.


1988 ◽  
Vol 135 (3) ◽  
pp. 161 ◽  
Author(s):  
M. Benaissa ◽  
A. Pajayakrit ◽  
S.S. Dlay ◽  
A.G.J. Holt
Keyword(s):  

1990 ◽  
Vol 137 (3) ◽  
pp. 225 ◽  
Author(s):  
J.-E. Chen ◽  
C.L. Lee ◽  
W.-Z. Shen
Keyword(s):  

Author(s):  
Kokoro KATO ◽  
Masakazu ENDO ◽  
Tadao INOUE ◽  
Shigetoshi NAKATAKE ◽  
Masaki YAMABE ◽  
...  
Keyword(s):  

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