Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

International Journal of Electronics ◽

10.1080/00207217.2014.982215 ◽

2014 ◽

Vol 102 (9) ◽

pp. 1486-1501 ◽

Author(s):

Bipin Kumar Verma ◽

Shyam Akashe ◽

Sanjay Sharma

Keyword(s):

Noise Reduction ◽

Low Leakage ◽

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Design of nano scale CMOS full adder with low leakage and ground bounce noise reduction

2016 International Conference on Signal Processing and Communication (ICSC) ◽

10.1109/icspcom.2016.7980610 ◽

2016 ◽

Author(s):

Candy Goyal ◽

Jagpal Singh Ubhi ◽

Balwinder Raj

Keyword(s):

Noise Reduction ◽

Low Leakage ◽

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Enhanced ground bounce noise reduction in low leakage CMOS multiplier cell

2016 International Conference on Research Advances in Integrated Navigation Systems (RAINS) ◽

10.1109/rains.2016.7764404 ◽

2016 ◽

Author(s):

R. H. Talwekar ◽

Nancy Bohra Jain

Keyword(s):

Noise Reduction ◽

Low Leakage ◽

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Ground bounce noise reduction of low leakage 1-bit nano-CMOS based full adder cells for mobile applications

2010 International Conference on Electronic Devices, Systems and Applications ◽

10.1109/icedsa.2010.5503106 ◽

2010 ◽

Author(s):

Manisha Pattanaik ◽

Muddala V. D. L. Varaprasad ◽

Fazal Rahim Khan

Keyword(s):

Noise Reduction ◽

Mobile Applications ◽

Low Leakage ◽

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Enhanced Ground Bounce Noise Reduction in a Low Leakage 90nm 1-Volt CMOS Full Adder Cell

2010 International Symposium on Electronic System Design ◽

10.1109/ised.2010.41 ◽

2010 ◽

Author(s):

M Pattanaik ◽

S Agnihotri ◽

M V D L Varaprashad ◽

T A Arasu

Keyword(s):

Noise Reduction ◽

Low Leakage ◽

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Four BIT CMOS full adder in submicron technology with low leakage and Ground bounce noise reduction

2012 International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2012.6188780 ◽

2012 ◽

Author(s):

H. V. Jayashree ◽

K. Harsha

Keyword(s):

Noise Reduction ◽

Low Leakage ◽

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Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

2012 International Symposium on Electronic System Design (ISED) ◽

10.1109/ised.2012.14 ◽

2012 ◽

Author(s):

Shashikant Sharma ◽

Manisha Pattanaik ◽

Balwinder Raj

Keyword(s):

Noise Reduction ◽

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A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

International Journal of Electronics ◽

10.1080/00207217.2014.996786 ◽

2015 ◽

Vol 102 (11) ◽

pp. 1852-1866 ◽

Author(s):

Vijay Kumar Sharma ◽

Manisha Pattanaik

Keyword(s):

Noise Reduction ◽

Reduction Technique ◽

Cmos Circuits ◽

Nanoscale Cmos ◽

Ground Bounce ◽

Noise Reduction Technique

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Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Frontiers of Optoelectronics ◽

10.1007/s12200-013-0328-8 ◽

2013 ◽

Vol 6 (3) ◽

pp. 327-337

Author(s):

Bipin Kumar Verma ◽

Shyam Babu Singh ◽

Shyam Akashe

Keyword(s):

Noise Reduction ◽

Cmos Circuits ◽

Nanoscale Cmos ◽

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Enhanced power gating schemes for low leakage low ground bounce noise in deep submicron circuits

2012 International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2012.6188736 ◽

2012 ◽

Author(s):

C. Saxena ◽

M. Pattanaik ◽

R. K. Tiwari

Keyword(s):

Deep Submicron ◽

Power Gating ◽

Low Leakage ◽

Ground Bounce ◽

Deep Submicron Circuits

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Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0144757 ◽

2012 ◽

Vol 1 (4) ◽

pp. 47-57

Author(s):

Chhavi Saxena

Keyword(s):

Noise Power ◽

Power Gating ◽

Low Leakage ◽

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