Design of nano scale CMOS full adder with low leakage and ground bounce noise reduction

2016 ◽  
Author(s):  
Candy Goyal ◽  
Jagpal Singh Ubhi ◽  
Balwinder Raj
Keyword(s):  
Noise Reduction ◽  
Full Adder ◽  
Nano Scale ◽  
Low Leakage ◽  
Ground Bounce

Enhanced Ground Bounce Noise Reduction in a Low Leakage 90nm 1-Volt CMOS Full Adder Cell

2010 ◽  
Author(s):  
M Pattanaik ◽  
S Agnihotri ◽  
M V D L Varaprashad ◽  
T A Arasu
Keyword(s):  
Noise Reduction ◽  
Full Adder ◽  
Low Leakage ◽  
Ground Bounce

scholarly journals NOVEL GROUND BOUNCE NOISE REDUCTION WITH ENHANCED POWER AND AREA EFFICIENCY FOR LOW POWER PORTABLE APPLICATION

2013 ◽  
pp. 280-282
Author(s):  
MOHD ABDUL SUMER ◽  
KADIYAM TIRUMALA RAO ◽  
PADALA SRINIVAS
Keyword(s):  
Mobile Applications ◽  
Heat Dissipation ◽  
Full Adder ◽  
Logic Circuits ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Area Efficiency ◽  
Low Leakage ◽  
Adiabatic Logic ◽  
Ground Bounce

As technology scales into the nanometer regime ground bounce noise and heat dissipation immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit PFAL full adder cells are proposed for mobile applications with low ground bounce noise and heat dissipation in the circuits using adiabatic logic. The simulations are done using DSCH &MicrowindSoftware.

Low Leakage Zero Ground Bounce Noise Nanoscale Full Adder Using Source Biasing Technique

2019 ◽  
Vol 14 (3) ◽  
pp. 360-370
Author(s):  
Candy Goyal ◽  
Jagpal Singh Ubhi ◽  
Balwinder Raj
Keyword(s):  
Full Adder ◽  
Low Leakage ◽  
Ground Bounce

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

2014 ◽  
Vol 102 (9) ◽  
pp. 1486-1501 ◽  
Author(s):  
Bipin Kumar Verma ◽  
Shyam Akashe ◽  
Sanjay Sharma
Keyword(s):  
Noise Reduction ◽  
Low Leakage ◽  
Ground Bounce

scholarly journals Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Farid Moshgelani ◽  
Dhamin Al-Khalili ◽  
Côme Rozon
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Power Supply ◽  
Full Adder ◽  
Arithmetic Circuits ◽  
University Of Florida ◽  
Low Leakage ◽  
The University

We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25 nm FinFET technology using the University of Florida UFDG model.

Process Variability Aware Low Leakage Reliable Nano Scale Double-Gate-FinFET SRAM Cell Design Technique

2015 ◽  
Vol 10 (6) ◽  
pp. 810-817 ◽  
Author(s):  
Saurabh Khandelwal ◽  
Vishal Gupta ◽  
Balwinder Raj ◽  
R. D. Gupta
Keyword(s):  
Double Gate ◽  
Cell Design ◽  
Design Technique ◽  
Process Variability ◽  
Nano Scale ◽  
Low Leakage ◽  
Sram Cell
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