Communication—Electron-Beam Stimulated Release of Dislocations from Pinning Sites in GaN

To achieve low leakage in GaN-based power devices and improve reliability in optoelectronic devices such as laser diodes, it is necessary to reduce dislocation density in epitaxial layers and control their introduction during processing. We have previously shown that dislocations can be introduced at room temperature in GaN. The effect of electron-beam irradiation at fixed points on the shift of such freshly introduced dislocations in GaN is reported. Dislocations can be displaced up to 10-15 µm from the beam position. We conclude the main reason limiting the dislocation travelling distance is the existence of a high number of pinning sites.

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

Hybrid La2O3-cPVP Dielectric for Organic Thin Film Transistor Applications

In this work, we have studied the electrical performance of cross-linked polyvinyl phenol (cPVP) modified lanthanum oxide (La2O3) bilayer dielectric film in pentacene thin film transistors (TFT). A simple spin-coating and room temperature operated cross-linking reaction of the hydroxyl moieties of PVP and the nitrogen groups of PMF were carried out to form the cross-linked PVP. The deposition of a thin 30 nm cPVP layer over the La2O3 layer provided a low leakage current (<10−7A/cm2), causing a reduction in the interface trap density. Besides, the modified surface properties of the La2O3 layer were favorable for the growth of pentacene organic semiconductors. As a result, the current on-off ratio and the sub-threshold slope was improved from 104 and 1.0 V/decade to 105 and 0.67 V/decade. The La2O3∕cPVP pentacene TFT operated at −10 V also exhibited improvement in the field-effect mobility to 0.71 cm2/Vs from 0.48 cm2/Vs for the single-layer La2O3 (130 nm) device. Thus, our work demonstrates that the rare earth oxide La2O3 with cPVP is an excellent dielectric system in the context of emerging transistors with hybrid polymer gate dielectrics.

Large-size (1.7 × 1.7 mm2) β-Ga2O3 field-plated trench MOS-type Schottky barrier diodes with 1.2 kV breakdown voltage and 109 high on/off current ratio

We fabricated high forward and low leakage current trench MOS-type Schottky barrier diodes (MOSSBDs) in combination with a field plate on a 12 μm thick epitaxial layer grown by halide vapor phase epitaxy on β-Ga2O3 (001) substrate. The MOSSBDs, measuring 1.7 × 1.7 mm2, exhibited a forward current of 2 A (70 A cm−2) at 2 V forward voltage and a leakage current of 5.7 × 10–10 A at −1.2 kV reverse voltage (on/off current ratio of > 109) with an ideality factor of 1.05 and wafer-level specific on-resistance of 17.1 mΩ · cm2.

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more compact and efficient in terms of battery consumption. The CMOS SRAMs have been replaced by the FinFET SRAMs due to the scaling limitations of the CMOS. Two FinFET SRAM cells have been which power efficient are and having high stability. Performance comparison of these cells has been done to analyze the leakage power and the static noise margins. The simulation of the cells is done at 20 nm FinFET technology. It has been analyzed that the write margin of improved 9T SRAM cell achieves an improvement of 1.49x. The read margin is also showing a drastic improvement over the existing cells which has been compared in the paper. The hold margin was found to be better in the case of the proposed SRAM cell at 0.4 V. The gate length has been varied to find the effect on read margin with gate length.

High polarization and wake-up free ferroelectric characteristics in ultrathin Hf0.5Zr0.5O2 devices by control of oxygen-deficient layer

The formation of an interfacial layer is believed to affect the ferroelectric properties in HfO2 based ferroelectric devices. The atomic layer deposited devices continue suffering from a poor bottom interfacial condition, since the formation of bottom interface is severely affected by atomic layer deposition (ALD) and annealing process. Herein, the formation of bottom interfacial layer was controlled through deposition of different bottom electrodes (BE) in device structure W/HZO/BE. The transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) analyses done on devices W/HZO/W and W/HZO/IrOx suggest the strong effect of IrOx in controlling bottom interfacial layer formation while W/HZO/W badly suffers from interfacial layer formation. W/HZO/IrOx devices show high remnant polarization (2Pr) ~ 53 µC/cm2, wake-up free endurance cycling characteristics, low leakage current with demonstration of low annealing temperature requirement as low as 350°C, valuable for BEOL integration. Further, sub-5 nm HZO thicknesses-based W/HZO/IrOx devices demonstrate high 2Pr and wake-up free ferroelectric characteristics, which can be promising for low power and high-density memory applications. 2.2 nm, 3 nm, and 4 nm HZO based W/HZO/IrOx devices show 2Pr values 13.54, 22.4, 38.23 µC/cm2 at 4 MV/cm and 19.96, 30.17, 48.34 µC/cm2 at 5 MV/cm, respectively, with demonstration of wake-up free ferroelectric characteristics.