scholarly journals Development of functional fault-tolerant system

2020 ◽  
Vol 1661 ◽  
pp. 012166
Author(s):  
K Zhigalov ◽  
S Yu Kuznetsova ◽  
M V Sygotina
2017 ◽  
Vol 26 (07) ◽  
pp. 1750111 ◽  
Author(s):  
Jie Wang ◽  
Jiwei Liu

The evolvable hardware (EHW) is widely used in the design of fault-tolerant system. Fault-tolerant system is really a real-time system, and the recovery time is necessary in fault detection and recovery. However, when applying EHW, real-time characteristic is usually ignored. In this paper, a fault-tolerant strategy based on EHW is proposed. The recovery time, predicted by the fault tree analysis (FTA), is considered as a constraint condition. A configuration library is set up in the design phase to accelerate the repair process of the anticipated faults. An evolvable algorithm (EA) based on similarity is applied to evolve the repair circuit for the unanticipated faults. When the library reaches the upper, the target system is reconfigured by the EA-repair technology. Extensive experiments are conducted to show that our method can improve the fault-tolerance of the system while satisfying the real-time requirement on FPGA platform. In a long run system, our method can keep a higher fault recovery rate.


2020 ◽  
Vol 65 (2) ◽  
pp. 66
Author(s):  
M. Petrescu ◽  
R. Petrescu

The implementation of a fault-tolerant system requires some type of consensus algorithm for correct operation. From Paxos to View-stamped Replication and Raft multiple algorithms have been developed to handle this problem. This paper presents and compares the Raft algorithm and Apache Kafka, a distributed messaging system which, although at a higher level, implements many concepts present in Raft (strong leadership, append-only log, log compaction, etc.).This shows that mechanisms conceived to handle one class of problems (consensus algorithms) are very useful to handle a larger category in the context of distributed systems.


2014 ◽  
pp. 26-30
Author(s):  
Goutam Kumar Saha

This paper examines a software implemented self-checking technique that is capable of detecting processorregisters' hardware-transient faults. The proposed approach is intended to detect run-time transient bit-errors in memory and processor status register. Error correction is not considered here. However, this low-cost approach is intended to be adopted in commodity systems that use ordinary off-the-shelf microprocessors, for the purpose of operational faults detection towards gaining fail-safe kind of fault tolerant system.


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