An improved hardware implementation of the fault-tolerant clock synchronization algorithm for large multiprocessor systems

1990 ◽  
Vol 39 (3) ◽  
pp. 404-407 ◽  
Author(s):  
B.-R. Choi ◽  
K.H. Park ◽  
M. Kim
10.29007/hq8s ◽  
2018 ◽  
Author(s):  
Sergiy Bogomolov ◽  
Christian Herrera ◽  
Wilfried Steiner

In this paper we propose a benchmark for verification of properties of fault-tolerantclock synchronization algorithms, namely, a benchmark of a TTEthernet network, whereproperties of the clock synchronization algorithm as implemented in a TTEthernet network can be verified, and optimization techniques for verification purposes can be applied.Our benchmark, which assumes non-faulty components, aims to be a basis for verifyingconfigurations which include faulty components, information consistency mechanisms, and for verifying other clock synchronization algorithms.


2014 ◽  
Vol 556-562 ◽  
pp. 4408-4411
Author(s):  
Chun Xu ◽  
Yue Lin ◽  
Ya Nan Gao ◽  
Song Tao Fan

An improved clock synchronization algorithm for time triggered architecture has been proposed in this paper. A single reference real time is added in the system, so periodically calibration to real time can be achieved. This algorithm is based on the classical Welch-Lynch[1] fault tolerant clock synchronization process. Systematic clock drift problem has been solved by using the algorithm. Formal analysis is presented, and verification is taken on Matlab/Simulink platform. Simulation result has verified the performance of the algorithm, and the clock difference is bounded as expected.


2021 ◽  
Vol 1815 (1) ◽  
pp. 012023
Author(s):  
Min Zhang ◽  
Linlin Duan ◽  
Kexian Gong ◽  
Xiaoyan Liu ◽  
Qian Cheng

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