Formal Analysis of a Distributed Fault Tolerant Clock Synchronization Algorithm for Automotive Communication Systems

An improved clock synchronization algorithm for time triggered architecture has been proposed in this paper. A single reference real time is added in the system, so periodically calibration to real time can be achieved. This algorithm is based on the classical Welch-Lynch[1] fault tolerant clock synchronization process. Systematic clock drift problem has been solved by using the algorithm. Formal analysis is presented, and verification is taken on Matlab/Simulink platform. Simulation result has verified the performance of the algorithm, and the clock difference is bounded as expected.

Download Full-text

An improved hardware implementation of the fault-tolerant clock synchronization algorithm for large multiprocessor systems

IEEE Transactions on Computers ◽

10.1109/12.48872 ◽

1990 ◽

Vol 39 (3) ◽

pp. 404-407 ◽

Cited By ~ 5

Author(s):

B.-R. Choi ◽

K.H. Park ◽

M. Kim

Keyword(s):

Hardware Implementation ◽

Fault Tolerant ◽

Clock Synchronization ◽

Multiprocessor Systems ◽

Synchronization Algorithm

Download Full-text

A practical implementation of the fault-tolerant Daisy-chain clock synchronization algorithm on CAN

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243872 ◽

2006 ◽

Cited By ~ 3

Author(s):

F.C. Carvalho ◽

C.E. Pereira ◽

E.T. Silva ◽

E.P. Freitas

Keyword(s):

Fault Tolerant ◽

Clock Synchronization ◽

Practical Implementation ◽

Synchronization Algorithm

Download Full-text

A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators

Lecture Notes in Computer Science - Dependable Computing — EDCC-3 ◽

10.1007/3-540-48254-7_8 ◽

1999 ◽

pp. 88-105 ◽

Cited By ~ 1

Author(s):

Henrik Lonn

Keyword(s):

Fault Tolerant ◽

Clock Synchronization ◽

Synchronization Algorithm

Download Full-text

Verification of Fault-Tolerant Clock Synchronization Algorithms

10.29007/hq8s ◽

2018 ◽

Author(s):

Sergiy Bogomolov ◽

Christian Herrera ◽

Wilfried Steiner

Keyword(s):

Fault Tolerant ◽

Clock Synchronization ◽

Optimization Techniques ◽

Synchronization Algorithm ◽

Information Consistency

In this paper we propose a benchmark for verification of properties of fault-tolerantclock synchronization algorithms, namely, a benchmark of a TTEthernet network, whereproperties of the clock synchronization algorithm as implemented in a TTEthernet network can be verified, and optimization techniques for verification purposes can be applied.Our benchmark, which assumes non-faulty components, aims to be a basis for verifyingconfigurations which include faulty components, information consistency mechanisms, and for verifying other clock synchronization algorithms.

Download Full-text