The Design of an IEEE 1588 End-to-End Transparent Ethernet Switch

<p>In measurement and control systems there is often a need to synchronise distributed clocks. Traditionally, synchronisation has been achieved using a dedicated medium to convey time information, typically using the IRIG-B serial protocol. The precision time protocol (IEEE 1588) has been designed as an improvement to current methods of synchronisation within a distributed network of devices. IEEE 1588 is a message based protocol that can be implemented across packet based networks including, but not limited to, Ethernet. Standard Ethernet switches introduce a variable delay to packets that inhibits path delay measurements. Transparent switches have been introduced to measure and adjust for packet delay, thus removing the negative effects that these variations cause. This thesis describes the hardware and firmware design of an IEEE 1588 transparent end-to-end Ethernet switch for Tekron International Ltd based in Lower Hutt, New Zealand. This switch has the ability to monitor all Ethernet traffic, identify IEEE 1588 timing packets, measure the delay that these packets experience while passing through the switch, and account for this delay by adjusting a time-interval field of the packet as it is leaving the switch. This process takes place at the operational speed of the port, and without introducing significant delay. Time-interval measurements can be made using a high-precision timestamp unit with a resolution of 1 ns. The total jitter introduced by this measurement process is just 4.5 ns through a single switch.</p>

The Design of an IEEE 1588 End-to-End Transparent Ethernet Switch

<p>In measurement and control systems there is often a need to synchronise distributed clocks. Traditionally, synchronisation has been achieved using a dedicated medium to convey time information, typically using the IRIG-B serial protocol. The precision time protocol (IEEE 1588) has been designed as an improvement to current methods of synchronisation within a distributed network of devices. IEEE 1588 is a message based protocol that can be implemented across packet based networks including, but not limited to, Ethernet. Standard Ethernet switches introduce a variable delay to packets that inhibits path delay measurements. Transparent switches have been introduced to measure and adjust for packet delay, thus removing the negative effects that these variations cause. This thesis describes the hardware and firmware design of an IEEE 1588 transparent end-to-end Ethernet switch for Tekron International Ltd based in Lower Hutt, New Zealand. This switch has the ability to monitor all Ethernet traffic, identify IEEE 1588 timing packets, measure the delay that these packets experience while passing through the switch, and account for this delay by adjusting a time-interval field of the packet as it is leaving the switch. This process takes place at the operational speed of the port, and without introducing significant delay. Time-interval measurements can be made using a high-precision timestamp unit with a resolution of 1 ns. The total jitter introduced by this measurement process is just 4.5 ns through a single switch.</p>

An optimization method of clock synchronization for large-scale regional power network based on IEEE 1588

At present, mobile devices generally use GPS, Beidou and other satellite time service methods to obtain time, but the clock synchronization based on IEEE 1588 protocol still has deviation. To solve this problem, a clock synchronization method is proposed to improve IEEE 1588 protocol. Based on the analysis of IEEE 1588 protocol, the clock deviation and frequency deviation which affect the synchronization accuracy are modeled. The second-order Kalman filtering algorithm is used to recursively deduce the clock deviation and frequency deviation, and the Allan variance is used to verify the noise characteristics and constantly correct the clock deviation. Finally, the improved effect is verified by relevant experiments. The results show that the improved system can improve the synchronization accuracy.

Sub-nanosecond synchronization implementation in pure Xilinx Kintex-7 FPGA

White Rabbit (WR) provides high-performance synchronization with sub-nanosecond accuracy and picoseconds precision, and it has been included in the new High Accuracy Default PTP Profile in the IEEE 1588-2019. As an open-source project, WR Precision Time Protocol (WR-PTP) core has been implemented in different FPGA platforms with dedicated clock circuits. This paper presents a novel approach to achieve the WR function in Xilinx Kintex-7 FPGA depending on the on-chip resource. This approach could achieve sub-nanosecond accuracy and tens of picoseconds precision, simplifying WR devices' hardware design and making it possible to port the WR PTP core to many mature hardware platforms.