Analysis and Simulation on Clock Resynchronization in Time Triggered Architecture
2014 ◽
Vol 556-562
◽
pp. 4408-4411
Keyword(s):
An improved clock synchronization algorithm for time triggered architecture has been proposed in this paper. A single reference real time is added in the system, so periodically calibration to real time can be achieved. This algorithm is based on the classical Welch-Lynch[1] fault tolerant clock synchronization process. Systematic clock drift problem has been solved by using the algorithm. Formal analysis is presented, and verification is taken on Matlab/Simulink platform. Simulation result has verified the performance of the algorithm, and the clock difference is bounded as expected.
Keyword(s):
2012 ◽
Vol 4
(8)
◽
pp. 181-189
2013 ◽
Vol 11
(6)
◽
pp. 2648-2652
Keyword(s):
2011 ◽
Vol 63-64
◽
pp. 905-910