A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell
2001 ◽
Vol 36
(4)
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pp. 666-675
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2008 ◽
Vol 2
(1)
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pp. 40
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2013 ◽
Vol E96.A
(8)
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pp. 1723-1729
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2018 ◽
Vol 6
(11)
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pp. 925-931
Keyword(s):
Keyword(s):