A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell

2001 ◽  
Vol 36 (4) ◽  
pp. 666-675 ◽  
Author(s):  
Perng-Fei Lin ◽  
J.B. Kuo
2008 ◽  
Vol 2 (1) ◽  
pp. 40 ◽  
Author(s):  
V. Chaudhary ◽  
T.-H. Chen ◽  
F. Sheerin ◽  
L.T. Clark

2022 ◽  
Vol 70 (3) ◽  
pp. 4583-4597
Author(s):  
Allam Abumwais ◽  
Adil Amirjanov ◽  
Kaan Uyar ◽  
Mujahed Eleyat

2016 ◽  
Vol E99.C (8) ◽  
pp. 936-946
Author(s):  
Ryotaro KOBAYASHI ◽  
Ikumi KANEKO ◽  
Hajime SHIMADA

2013 ◽  
Vol 2 (3) ◽  
pp. 24-29
Author(s):  
D. Pradeep ◽  
◽  
B. Ananda Venkatesan ◽  

Sign in / Sign up

Export Citation Format

Share Document