scholarly journals Dual-Port Content Addressable Memory for Cache Memory Applications

2022 ◽  
Vol 70 (3) ◽  
pp. 4583-4597
Author(s):  
Allam Abumwais ◽  
Adil Amirjanov ◽  
Kaan Uyar ◽  
Mujahed Eleyat
Keyword(s):  
Cache Memory ◽  
Content Addressable Memory ◽  
Memory Applications

Critical race-free low-power NAND match line content addressable memory tagged cache memory

2008 ◽  
Vol 2 (1) ◽  
pp. 40 ◽  
Author(s):  
V. Chaudhary ◽  
T.-H. Chen ◽  
F. Sheerin ◽  
L.T. Clark
Keyword(s):  
Low Power ◽  
Cache Memory ◽  
Critical Race ◽  
Content Addressable Memory

MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

2022 ◽  
Vol 27 (2) ◽  
pp. 1-18
Author(s):  
Shaahin Angizi ◽  
Navid Khoshavi ◽  
Andrew Marshall ◽  
Peter Dowben ◽  
Deliang Fan
Keyword(s):  
High Speed ◽  
Memory Cell ◽  
Low Power Design ◽  
Evaluation Framework ◽  
Cache Memory ◽  
Array Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memory Applications ◽  
First Time

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

Integration of STT-MRAMs for Embedded Cache Memories

2014 ◽  
Vol 95 ◽  
pp. 146-149
Author(s):  
Toshihiro Sugii ◽  
Yoshihisa Iba ◽  
Masaki Aoki ◽  
Hideyuki Noshiro ◽  
Kouji Tsunoda ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Magnetic Tunnel Junction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Cache Memory ◽  
Current Status ◽  
Cache Memories ◽  
Time Dependent Dielectric Breakdown ◽  
Memory Applications ◽  
Embedded Sram

We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration with the back-end-of-line (BEOL) process to replace conventional embedded SRAM cache memories. Our MRAM technology features a top-pinned, perpendicular magnetic tunnel junction (MTJ) and a highly reliable MTJ for a cache memory. We could obtain a higher density cache memory than that with conventional SRAMs with our STT-MRAMs, and leakage free characteristics, as well as unlimited write and read cycling times and 10-year time-dependent dielectric breakdown (TDDB) characteristics. They were integrated into Cu interconnects with 300 mm facilities. We also discuss variations in MTJ pattern sizes that are very important for memory applications from the viewpoint of high density embedded cache memories.

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

2012 ◽  
Vol 43 (11) ◽  
pp. 766-792 ◽  
Author(s):  
Arash Azizi Mazreah ◽  
M.T. Manzuri Shalmani
Keyword(s):  
Soft Error ◽  
Cache Memory ◽  
Low Leakage ◽  
Memory Applications

Pt/Cu:ZnO/Nb:STO memristive dual port for cache memory applications

2020 ◽  
Author(s):  
Pavan Kumar Reddy Boppidi ◽  
S. Siddhartha Raman ◽  
H. Renuka ◽  
Souvik Kundu
Keyword(s):  
Cache Memory ◽  
Memory Applications

Investigation of ferroelectrics using conventional and in situ electron microscopy

1994 ◽  
Vol 52 ◽  
pp. 586-587
Author(s):  
V. Saikumar ◽  
H. M. Chan ◽  
M. P. Harmer
Keyword(s):  
Nonvolatile Memory ◽  
Ferroelectric Materials ◽  
Gate Insulator ◽  
Sensors And Actuators ◽  
In Situ Electron Microscopy ◽  
Ferroelectric Domains ◽  
Domain Boundaries ◽  
Domain Interactions ◽  
Memory Applications

In recent years, there has been a growing interest in the application of ferroelectric thin films for nonvolatile memory applications and as a gate insulator in DRAM structures. In addition, bulk ferroelectric materials are also widely used as components in electronic circuits and find numerous applications in sensors and actuators. To a large extent, the performance of ferroelectric materials are governed by the ferroelectric domains (with dimensions in the micron to sub-micron range) and the switching of domains in the presence of an applied field. Conventional TEM studies of ferroelectric domains structures, in conjunction with in-situ studies of the domain interactions can aid in explaining the behavior of ferroelectric materials, while providing some answers to the mechanisms and processes that influence the performance of ferroelectric materials. A few examples from bulk and thin film ferroelectric materials studied using the TEM are discussed below.Figure 1 shows micrographs of ferroelectric domains obtained from undoped and Fe-doped BaTiO3 single crystals. The domain boundaries have been identified as 90° domains with the boundaries parallel to <011>.

Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences

2016 ◽  
Vol E99.C (8) ◽  
pp. 936-946
Author(s):  
Ryotaro KOBAYASHI ◽  
Ikumi KANEKO ◽  
Hajime SHIMADA
Keyword(s):  
Utilization Efficiency ◽  
Cache Memory ◽  
Data Utilization
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