CASSE: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip

2004 ◽  
Author(s):  
V. Reyes ◽  
T. Bautista ◽  
G. Marrero ◽  
P.P. Carballo ◽  
W. Kruijtzer
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
System Level ◽  
Multiprocessor Systems ◽  
System Level Modeling ◽  
Systems On Chip ◽  
Exploration Tool ◽  
On Chip

A correlation-based design space exploration methodology for multi-processor systems-on-chip

2010 ◽  
Author(s):  
Giovanni Mariani ◽  
Aleksandar Brankovic ◽  
Gianluca Palermo ◽  
Jovana Jovic ◽  
Vittorio Zaccaria ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Systems On Chip ◽  
On Chip

scholarly journals A Signature-Based Power Model for MPSoC on FPGA

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Roberta Piscitelli ◽  
Andy D. Pimentel
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Power Estimation ◽  
System Level ◽  
Estimation Methods ◽  
Instruction Set ◽  
Systems On Chip ◽  
Event Signatures ◽  
On Chip ◽  
High Level

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

2012 ◽  
pp. 263-277
Author(s):  
Sanna Määttä ◽  
Leandro Möller ◽  
Leandro Soares Indrusiak ◽  
Luciano Ost ◽  
Manfred Glesner ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Space Exploration ◽  
Network On Chip ◽  
Multiprocessor Systems ◽  
Trade Off ◽  
Successive Refinement ◽  
Systems On Chip ◽  
On Chip ◽  
Abstraction Levels

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

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