E/D Mode Logic Cells and Series-to-Parallel Interface with Less Transistors and Better Structure Consistence in GaAs Process

2021 ◽  
Author(s):  
Shijie Chen ◽  
Tao Yang ◽  
Xiang Li ◽  
Jian Yang ◽  
Liang Qi ◽  
...  
Keyword(s):  
Logic Cells ◽  
Parallel Interface

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS

2010 ◽  
Author(s):  
Frank O'Mahony ◽  
Joseph Kennedy ◽  
James E. Jaussi ◽  
Ganesh Balamurugan ◽  
Mozhgan Mansuri ◽  
...  
Keyword(s):  
Parallel Interface

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

2015 ◽  
Author(s):  
Timothy O. Dickson ◽  
Yong Liu ◽  
Ankur Agrawal ◽  
John F. Bulzacchelli ◽  
Herschel Ainspan ◽  
...  
Keyword(s):  
Parallel Interface ◽  
Soi Cmos

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

2006 ◽  
Vol 22 (2) ◽  
pp. 161-172 ◽  
Author(s):  
Patrick Girard ◽  
Olivier Héron ◽  
Serge Pravossoudovitch ◽  
Michel Renovell
Keyword(s):  
Delay Faults ◽  
Logic Cells

Low Energy, Low Power Adder Logic Cells: A CMOS VLSI Implementation

2014 ◽  
Vol 7 (2) ◽  
pp. 248-255 ◽  
Author(s):  
S. Hari Hara Subramani ◽  
K.S.S.K. Rajesh ◽  
V. Elamaran
Keyword(s):  
Low Power ◽  
Low Energy ◽  
Vlsi Implementation ◽  
Logic Cells ◽  
Cmos Vlsi
Sign in / Sign up

Export Citation Format

Share Document