Multichannel ADC IP Core on Xilinx SoC FPGA

Sensing of analogue signals such as voltage, temperature, pressure, current etc. is required to acquire the real time analog signals in the form digital streams. Most of the static analog signals are converted into voltage using sensors, transducers etc. and then measured using ADCs. The digitized samples from ADC are collected either through serial or parallel interface and processed by the programmable chips such as processors, controllers, FPGAs, SOCs etc. In some cases, Multichannel supported ADCs are used to save the layout area when the functionalities are to be realized in a small form factor. In such scenarios, parallel interface for each channel is not a preferred interface considering the more number of interfaces / traces between the components. Hence, Custom, Sink synchronized, Configurable multichannel ADC soft IP core has been developed using VHDL coding to interwork with multichannel supported, time division multiplexed ADCs with serial interface. The developed IP core can be used either as it is with the SPI interface as specified in this paper or with necessary modifications / configurations. The configurations can be the number of channels, sample size, sampling frequency, data transfer clock, type of synchronization – source / sink, control signals and the sequence of the operations performed to configure ADC. The efficiency of implementation is validated using the measurements of throughput, and accuracy for the required range of input with acceptable tolerances. ZYNQ FPGA and LTC2358 ADC are used to evaluate the developed IP core. Integrated Logic Analyser (ILA) which is an integrated verification tool of Vivado is used for Verification.

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

Microwave core-chips are highly integrated MMICs that are in charge of all the beam-shaping functions of a transmit-receive module within a phased array system. Such chips include switches, amplifiers and attenuators, phase shifters, and possibly other elements, each to be controlled by external digital signals. Given the large number of control lines to be integrated in a core-chip, the embedding of a serial to parallel interface is indispensable. Digital design in compound semiconductor technology is still rather challenging due to the absence of complementary devices and the availability of a limited number of metallization layers. Moreover, in large arrays, high chip yield and repeatability are required. This paper discusses and compares challenges and solutions for the key sub-circuits of GaAs serial to parallel converters for core-chip applications, reviewing the pros and cons of the different implementations proposed in the literature.

ENERGY AND ECOLOGICAL ASPECTS OF ROASTING OF BULK LIGHTWEIGHT MATERIALS IN ELECTRIC FURNACES

The article studies the energy and ecological aspects of the process of roasting of vermiculite and other lightweight materials in electric modular-firing furnaces which are alternatives to fired furnaces using hydrocarbon fuel. A double industrial electric furnace with a series-parallel interface of modules having auxiliary equipment is described. It forms a technological system for processing vermiculite concentrates and conglomerates. Energy and environmental performance indicators (efficiency, heat losses, and specific energy intensity) are assessed for these types of furnaces. The methods for collecting and accumulating useful resources – finely dispersed materials formed when vermiculite swells in new electric furnaces – are described.

Design of domestic serial and parallel interface module

Domestic serial and parallel interface module is based on domestic high performance FPGA CPCIE module. This type of FPGA has rich logical resources and internal integration of a variety of high-speed interfaces, such as PCIE, high-speed Serdes interface, which can achieve serial port, time system, network and other interfaces design, greatly simplifying the hardware design of the module. The main communication interfaces, PCIE and UART, are realized by the IP core of FPGA, realizing the integration of the main functions on the chip, which greatly improves the flexibility and expansibility of the design.

Characterization of Fine-Pitch Interconnections (≤ 10 μm) on Silicon Interconnect Fabric for Heterogeneous Integration

We propose a fine-pitch, highly scalable, heterogeneous integration platform called the Silicon-Interconnect Fabric (Si-IF) where dielets are assembled with fine-pitch interconnects (≤ 10 μm) at short inter-dielet spacings (≤ 100 μm) using direct metal-metal Thermal Compression Bonding process (TCB). As a result, short links on Si-IF (≤ 500 μm) are used for inter-dielet communication, reducing the latency to ≤ 35 ps. We experimentally demonstrated the measured insertion loss in these short Si-IF links (≤ 500 μm) is ≤ 2 dB for frequencies up to 30 GHz. Consequently, we show that assemblies on Si-IF have 10–40X lower parasitic inductance, and 7–35X lower parasitic capacitance compared to assemblies on interposers and PCBs. We propose the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol for data transfer that efficiently utilizes the Si-IF to achieve data-rates of ≥ 10 Gbps/link at an energy/bit of ≤ 0.04 pJ/b. Further, the aggregate bandwidth/mm is ≥ 8 Tbps/mm. This corresponds to an improvement of 120–300X in bandwidth/mm and a reduction of 100–500X in energy/bit compared to conventional systems.