GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators

Mapping Intimacies ◽

10.1109/ats52891.2021.00034 ◽

2021 ◽

Author(s):

Stefan Holst ◽

Lim Bumun ◽

Xiaoqing Wen

Keyword(s):

Systolic Array ◽

Timing Simulation

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Bi-way sorter. a two-dimensional systolic array

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1992.0024 ◽

1992 ◽

Vol 139 (2) ◽

pp. 147

Author(s):

G.A. Orton ◽

L.E. Peppard ◽

S.G. Akl

Keyword(s):

Systolic Array ◽

Two Dimensional

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Redundancy design for a fault tolerant systolic array

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1990.0027 ◽

1990 ◽

Vol 137 (3) ◽

pp. 218 ◽

Author(s):

J.-J. Wang ◽

C.-W. Jen

Keyword(s):

Systolic Array ◽

Fault Tolerant ◽

Redundancy Design

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Two-mode adaptive beamformer using a systolic array

IEE Proceedings F Radar and Signal Processing ◽

10.1049/ip-f-2.1991.0063 ◽

1991 ◽

Vol 138 (5) ◽

pp. 483

Author(s):

K. Takao ◽

C.S. Boon

Keyword(s):

Systolic Array ◽

Adaptive Beamformer

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Systolic Array Adaptive Beamforming

10.21236/ada187496 ◽

1987 ◽

Author(s):

Norman L. Owsley

Keyword(s):

Systolic Array ◽

Adaptive Beamforming

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Erratum: Novel systolic array realisation of allpass digital filters for high speed applications

Electronics Letters ◽

10.1049/el:19921182 ◽

1992 ◽

Vol 28 (19) ◽

pp. 1852

Author(s):

H.K. Kwan

Keyword(s):

Systolic Array ◽

Digital Filters

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Test Architecture for Systolic Array of Edge-based AI Accelerator

IEEE Access ◽

10.1109/access.2021.3094741 ◽

2021 ◽

pp. 1-1

Author(s):

Umair Saeed Solangi ◽

Muhammad Ibtesam ◽

Muhammad Adil Ansari ◽

Jinuk Kim ◽

Sungju Park

Keyword(s):

Systolic Array ◽

Test Architecture

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Improved Design and Analyse of Parallel Matrix Multiplication on Systolic Array Matrix

2009 International Conference on Computational Intelligence and Software Engineering ◽

10.1109/cise.2009.5366384 ◽

2009 ◽

Author(s):

Feifei Dong ◽

Sihan Zhang ◽

Cheng Chen

Keyword(s):

Systolic Array ◽

Matrix Multiplication ◽

Improved Design

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An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention

2021 IEEE 39th VLSI Test Symposium (VTS) ◽

10.1109/vts50974.2021.9441004 ◽

2021 ◽

Author(s):

Ning-Chi Huang ◽

Wei-Kai Tseng ◽

Huan-Jan Chou ◽

Kai-Chiang Wu

Keyword(s):

Systolic Array ◽

Energy Efficient ◽

Error Prediction ◽

Timing Error ◽

Prediction And Prevention

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Verification of systolic array: An FP functional approach

Journal of Computer Science and Technology ◽

10.1007/bf02943335 ◽

1988 ◽

Vol 3 (2) ◽

pp. 81-101

Author(s):

Yongqiang Sun

Keyword(s):

Systolic Array ◽

Functional Approach

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Finite word-length effects of an unified systolic array for 2-D DCT/IDCT

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542799 ◽

2002 ◽

Author(s):

H. Lim ◽

C. Yim ◽

E.E. Swartzlander

Keyword(s):

Systolic Array ◽

Word Length ◽

Finite Word Length ◽

Finite Word ◽

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