PLAGA: a highly parallelizable genetic algorithm for programmable logic arrays test pattern generation

Proceedings of the 1999 Congress on Evolutionary Computation-CEC99 (Cat. No. 99TH8406) ◽

10.1109/cec.1999.782524 ◽

2003 ◽

Author(s):

A. Cruz ◽

S. Mukherjee

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Programmable Logic ◽

Programmable Logic Arrays

Download Full-text

Crosstalk Test Pattern Generation for Dynamic Programmable Logic Arrays

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2006.877721 ◽

2006 ◽

Vol 55 (4) ◽

pp. 1288-1302 ◽

Author(s):

J. Liu ◽

W.-B. Jone ◽

S.R. Das

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Programmable Logic ◽

Programmable Logic Arrays

Download Full-text

PLABEK: a complete automatic test pattern generation system for break faults in programmable logic arrays

1995 International Symposium on VLSI Technology Systems and Applications Proceedings of Technical Papers VTSA-95 ◽

10.1109/vtsa.1995.524639 ◽

2002 ◽

Author(s):

Gwo-Haur Hwang ◽

Wen-Zen Shen ◽

Shing Tenqchen

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Programmable Logic ◽

Generation System ◽

Programmable Logic Arrays ◽

Download Full-text

Crosstalk Test Pattern Generation for Dynamic Programmable Logic Arrays

2005 IEEE Instrumentationand Measurement Technology Conference Proceedings ◽

10.1109/imtc.2005.1604067 ◽

2006 ◽

Author(s):

J. Liu ◽

W.B. Jone ◽

S.R. Das

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Programmable Logic ◽

Programmable Logic Arrays

Download Full-text

Fault analysis and automatic test pattern generation for break faults in programmable logic arrays

IEE Proceedings - Circuits Devices and Systems ◽

10.1049/ip-cds:19960267 ◽

1996 ◽

Vol 143 (3) ◽

pp. 157 ◽

Author(s):

G.-H. Hwang ◽

W.-Z. Shen

Keyword(s):

Test Pattern ◽

Fault Analysis ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Programmable Logic ◽

Programmable Logic Arrays ◽

Download Full-text

Product-oriented test-pattern generation for Programmable Logic Arrays

Journal of Computer Science and Technology ◽

10.1007/bf02943422 ◽

1990 ◽

Vol 5 (2) ◽

pp. 164-174

Author(s):

Jintao Li ◽

Yinghua Min

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Programmable Logic ◽

Programmable Logic Arrays

Download Full-text

Hierarchical test pattern generation using a genetic algorithm with a dynamic global reference table

10.1049/cp:19951101 ◽

1995 ◽

Author(s):

M.J. O'Dare

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Reference Table

Download Full-text

Test pattern generation for worst-case crosstalk faults in DSM chips using Genetic Algorithm

2008 2nd Electronics Systemintegration Technology Conference ◽

10.1109/estc.2008.4684381 ◽

2008 ◽

Author(s):

K.K. Duganapalli ◽

A.K. Palit ◽

W. Anheier

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Download Full-text

GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.511578 ◽

1996 ◽

Vol 15 (8) ◽

pp. 991-1000 ◽

Author(s):

F. Corno ◽

P. Prinetto ◽

M. Rebaudengo ◽

M. Sonza Reorda

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Sequential Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Automatic Test ◽

Synchronous Sequential Circuits

Download Full-text

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

2014 International Conference on Electronics and Communication Systems (ICECS) ◽

10.1109/ecs.2014.6892760 ◽

2014 ◽

Author(s):

J. P. Anita ◽

P. T. Vanathi

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Vlsi Circuits ◽

Test Pattern Generation ◽

Test Power Reduction

Download Full-text

A novel specification based test pattern generation using genetic algorithm and wavelets

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design ◽

10.1109/icvd.2005.28 ◽

2005 ◽

Author(s):

P. Kalpana ◽

K. Gunavathi

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation

Download Full-text