test power reduction Latest Research Papers

An Improved Test Pattern Reordering Framework Targeting Test Power Reduction

10.1109/itcindia52672.2021.9532684 ◽

2021 ◽

Author(s):

Hillol Maity ◽

Santanu Chattopadhyay ◽

Indranil Sengupta ◽

Parthajit Bhattacharya ◽

Girish Patankar

Keyword(s):

Test Pattern ◽

Power Reduction ◽

Test Power ◽

Test Power Reduction

A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2020.3004371 ◽

2020 ◽

Vol 67 (12) ◽

pp. 3432-3436

Author(s):

Sangjun Lee ◽

Kyunghwan Cho ◽

Sungki Choi ◽

Sungho Kang

Keyword(s):

Power Reduction ◽

Test Power ◽

Test Power Reduction ◽

Scan Chain ◽

Logic Topology

Design and Implementation of Novel Scan Architecture for Test Power Reduction

Procedia Computer Science ◽

10.1016/j.procs.2020.04.277 ◽

2020 ◽

Vol 171 ◽

pp. 2556-2562

Author(s):

Harshavardhan Nekar ◽

Saroja V. Siddamal

Keyword(s):

Power Reduction ◽

Test Power ◽

Design And Implementation ◽

Test Power Reduction

Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI) ◽

10.1109/icoei.2019.8862751 ◽

2019 ◽

Author(s):

Ch. Narasimha Kumar ◽

A. Madhumitha ◽

N. Sesi Preetam ◽

P. Vamsi Gupta ◽

J.P. Anita

Keyword(s):

Fault Diagnosis ◽

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Reduction Technique ◽

Vlsi Circuits ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Test Power ◽

Test Power Reduction

Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency

International Journal of Engineering ◽

10.5829/ije.2018.31.05b.10 ◽

2018 ◽

Vol 31 (5) ◽

Keyword(s):

Power Reduction ◽

Test Power ◽

Test Power Reduction

A stochastic heuristic based approach to test vector reordering for dynamic test power reduction

2016 2nd International Conference on Contemporary Computing and Informatics (IC3I) ◽

10.1109/ic3i.2016.7918020 ◽

2016 ◽

Author(s):

Sanjoy Mitra ◽

Debaprasad Das

Keyword(s):

Dynamic Test ◽

Power Reduction ◽

Test Vector ◽

Test Power ◽

Test Power Reduction

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

International Journal of High Performance Systems Architecture ◽

10.1504/ijhpsa.2016.076204 ◽

2016 ◽

Vol 6 (1) ◽

pp. 51 ◽

Cited By ~ 3

Author(s):

J.P. Anita ◽

P. Sudheesh

Keyword(s):

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Test Pattern Generation ◽

Decision Diagrams ◽

Test Power ◽

Multiple Faults ◽

Test Power Reduction

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

IEICE Transactions on Information and Systems ◽

10.1587/transinf.2015edp7289 ◽

2016 ◽

Vol E99.D (11) ◽

pp. 2672-2681 ◽

Cited By ~ 1

Author(s):

Tian CHEN ◽

Dandan SHEN ◽

Xin YI ◽

Huaguo LIANG ◽

Xiaoqing WEN ◽

...

Keyword(s):

Power Reduction ◽

Test Power ◽

Test Compression ◽

Test Power Reduction

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

2014 International Conference on Electronics and Communication Systems (ICECS) ◽

10.1109/ecs.2014.6892760 ◽

2014 ◽

Cited By ~ 4

Author(s):

J. P. Anita ◽

P. T. Vanathi

Keyword(s):

Genetic Algorithm ◽

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Vlsi Circuits ◽

Test Pattern Generation ◽

Test Power ◽

Test Power Reduction

Scan chain swapping using TSVs for test power reduction in 3D-IC

2013 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2013.6863963 ◽

2013 ◽

Author(s):

Ingeol Lee ◽

Jaeseok Park ◽

Sungho Kang

Keyword(s):

Power Reduction ◽

Test Power ◽

3D Ic ◽

Test Power Reduction ◽

Scan Chain

test power reduction
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

An Improved Test Pattern Reordering Framework Targeting Test Power Reduction

A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction

Design and Implementation of Novel Scan Architecture for Test Power Reduction

Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency

A stochastic heuristic based approach to test vector reordering for dynamic test power reduction

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

Scan chain swapping using TSVs for test power reduction in 3D-IC

Export Citation Format

test power reductionRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

An Improved Test Pattern Reordering Framework Targeting Test Power Reduction

A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction

Design and Implementation of Novel Scan Architecture for Test Power Reduction

Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency

A stochastic heuristic based approach to test vector reordering for dynamic test power reduction

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

Scan chain swapping using TSVs for test power reduction in 3D-IC

test power reduction
Recently Published Documents