Optimized design of full-subtractor using new SRG reversible logic gates and VHDL simulation

2015 ◽  
Author(s):  
Md. Samiur Rahman ◽  
Sajjad Waheed ◽  
Ali Newaz Bahar
Keyword(s):  
Logic Gates ◽  
Reversible Logic ◽  
Optimized Design ◽  
Reversible Logic Gates

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

2018 ◽  
Vol 16 (02) ◽  
pp. 1850016 ◽  
Author(s):  
H. Maity ◽  
A. Biswas ◽  
A. K. Bhattacharjee ◽  
A. Pal
Keyword(s):  
Quantum Computing ◽  
Logic Gate ◽  
Logic Gates ◽  
Reversible Logic ◽  
Shift Register ◽  
Optimized Design ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Reversible Logic Gates

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Design of a Power Efficient ALU Using Reversible Logic Gates

2018 ◽  
pp. 469-479
Author(s):  
B. Abdul Rahim ◽  
B. Dhananjaya ◽  
S. Fahimuddin ◽  
N. Bala Dastagiri
Keyword(s):  
Logic Gates ◽  
Reversible Logic ◽  
Power Efficient ◽  
Reversible Logic Gates
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