Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18-µm CMOS technology

Circuits for CMOS two-dimensional (2-D) array data transfer are indispensable for applications such as space and nuclear fields. Issues include to be operated with higher speed, lower power, fewer size penalty and radiation hardness. To meet these requirements, two kinds of CMOS 2-D array data transfer circuits, such as a shift register type and a memory access type, are proposed and fabricated by the standard 0.18-µm CMOS process technology. In the both types, 16 µm pitch, 8×124 array data transfer operations were realized with data rate of more than 1 Gb/s. Furthermore, we conducted 60Co γ-ray irradiation experiments on those circuits. The current consumption ratio of the shift register type to the memory access type ranges from 150 to 200% as the dosage increases. The result indicate that the memory access type has better radiation hardness at 1 Gb/s than that of the shift register type.

Finding Non-liner Register on Binary M-Sequence Generating Binary Multiplication Sequence

In the current time there is an important problem that is for a received linear or nonlinear binary sequence {zn} how we can find the nonlinear feedback shift register and its linear equivalent which generate this sequence. The linear orthogonal sequences, special M-Sequences, play a big role in these methods for solving this problem. In the current research trying give illuminations about the methods which are very useful for solving this problem under short sequences, and study these methods for finding the nonlinear feedback shift register of a multiplication sequence and its linear equivalent feedback shift register of a received multiplication binary sequence{zn} where the multiplication on h degrees of a binary linear sequence {an}, or finding the equivalent linear feedback shift register of {zn}, where the sequence {zn}of the form M-sequence, and these methods are very effectively. We can extend these methods for the large sequences using programming and modern computers with large memory.

Linear Feedback Shift Register and its Applications in Digital System Design

In digital system design, the Linear Feedback Shift Register (LFSR) is the queen of logic functions, and the design engineers can use LFSR in both hardware (HW) or software (SW) implementation. In this paper, LFSR will be discussed in its HW implementation via Hardware description language. In addition, the application of LFSR in of pseudorandom number generator (PRNG), direct sequence spread spectrum (DSSS), cyclic redundancy check (CRC) is also given. Keywords-- Digital system design, System on chip, ASIC digital design, Linear feedback shift register

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT‑LFSR‑TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.