Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

2018 ◽  
Vol 16 (02) ◽  
pp. 1850016 ◽  
Author(s):  
H. Maity ◽  
A. Biswas ◽  
A. K. Bhattacharjee ◽  
A. Pal
Keyword(s):  
Quantum Computing ◽  
Logic Gate ◽  
Logic Gates ◽  
Reversible Logic ◽  
Shift Register ◽  
Optimized Design ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Reversible Logic Gates

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

scholarly journals High functionality reversible arithmetic logic unit

2020 ◽  
Vol 10 (3) ◽  
pp. 2329
Author(s):  
Shaveta Thakral ◽  
Dipali Bansal
Keyword(s):  
Power Dissipation ◽  
Logic Gates ◽  
Reversible Logic ◽  
Logic Design ◽  
Quantum Cost ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Reversible Logic Gates ◽  
Reversible Alu ◽  
Logic Unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

2020 ◽  
Vol 12 (3) ◽  
pp. 146-148
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Arup K. Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Quantum Circuit ◽  
Reversible Logic ◽  
Optimized Design ◽  
Quantum Cost ◽  
Constant Input ◽  
Logic Block ◽  
Reversible Gate ◽  
Garbage Output

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Novel design of multiplexer and demultiplexer using reversible logic gates

2018 ◽  
Vol 7 (3.29) ◽  
pp. 80
Author(s):  
Veerendra Nath Nune ◽  
Addanki Purna R
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Logic Gates ◽  
Novel Design

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.  

scholarly journals A review on reversible logic gates

2020 ◽  
Vol 12 (1) ◽  
pp. 242-250
Author(s):  
B.Y. Galadima ◽  
G.S.M. Galadanci ◽  
A. Tijjani ◽  
M. Ibrahim
Keyword(s):  
Digital Signal ◽  
Logic Gates ◽  
Propagation Delay ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Comparative Review ◽  
Reversible Logic Gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,

scholarly journals Design and Implementation of PERES based 128 bit Parallel Adder using FPGA

2019 ◽  
Vol 9 (2) ◽  
pp. 2984-2988
Keyword(s):  
Parallel Processing ◽  
Logic Gate ◽  
Logic Gates ◽  
Cost Effective ◽  
Reversible Logic ◽  
Unique Property ◽  
Simulation Design ◽  
Design And Implementation ◽  
Input And Output ◽  
Reversible Logic Gates

In this work, the parallel adder is designed using the PERES reversible logic gate with the resolution of 128 bits. The reversible logic gates have a unique property of one to one mapping between the input and output vectors. The simulation design is verified using the NI lab view tool for the resolution of 24 bits. For higher resolution designs, the HDL code is developed by making use of the Xilinx Spartan FPGA device. The HDL has several advantages like parallel processing, design compatibility, cost effective, reconfigurable, versatile language and design hierarchy. The performance of the proposed method is validated by comparing the area and power consumption with two FPGA devices.

Design of Reversible Shift Register Using Reduced Number of Logic Gates

2020 ◽  
Vol 12 (1) ◽  
pp. 33-37
Author(s):  
Heranmoy Maity ◽  
Sudipta Banerjee ◽  
Arindam Biswas ◽  
Anita Pal ◽  
Anup Kumar Bhattacharjee
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Low Power Design ◽  
Reversible Logic ◽  
Vlsi Circuits ◽  
Shift Register ◽  
Proposed Model ◽  
Low Power Dissipation ◽  
Reversible Logic Gates

Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

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