Fast Fuzzy C-Means Clustering Based on Low-Cost High-Performance VLSI Architecture in Reconfigurable Hardware

2010 ◽  
Author(s):  
Yao-Jung Yeh ◽  
Hui-Ya Li ◽  
Cheng-Yen Yang ◽  
Wen-Jyi Hwang
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Vlsi Architecture ◽  
Reconfigurable Hardware ◽  
Fuzzy C Means ◽  
Fuzzy C Means Clustering

scholarly journals VLSI Implementation of a High-Performance Nonlinear Image Scaling Algorithm

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Osamah Ibrahim Khalaf ◽  
Carlos Andrés Tavera Romero ◽  
A. Azhagu Jaisudhan Pazhani ◽  
G. Vinuja
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Vlsi Architecture ◽  
Linear Interpolation ◽  
Noisy Environments ◽  
Image Scaling ◽  
Scaling Methods ◽  
Processing Resources ◽  
Weighted Median ◽  
Memory Efficient

This study implements the VLSI architecture for nonlinear-based picture scaling that is minimal in complexity and memory efficient. Image scaling is used to increase or decrease the size of an image in order to map the resolution of different devices, particularly cameras and printers. Larger memory and greater power are also necessary to produce high-resolution photographs. As a result, the goal of this project is to create a memory-efficient low-power image scaling methodology based on the effective weighted median interpolation methodology. Prefiltering is employed in linear interpolation scaling methods to improve the visual quality of the scaled image in noisy environments. By decreasing the blurring effect, the prefilter performs smoothing and sharpening processes to produce high-quality scaled images. Despite the fact that prefiltering requires more processing resources, the suggested solution scales via effective weighted median interpolation, which reduces noise intrinsically. As a result, a low-cost VLSI architecture can be created. The results of simulations reveal that the effective weighted median interpolation outperforms other existing approaches.

Implementation and Comparative Analysis of k-means and Fuzzy c-means Clustering Algorithms for Tasks Allocation in Distributed Real Time System

2019 ◽  
Vol 10 (2) ◽  
pp. 66-86 ◽  
Author(s):  
Harendra Kumar ◽  
Isha Tyagi
Keyword(s):  
Real Time ◽  
High Performance ◽  
Distributed Processing ◽  
Clustering Algorithms ◽  
Processing System ◽  
Real Time Systems ◽  
Real Time System ◽  
Fuzzy C Means ◽  
Fuzzy C Means Clustering ◽  
Time Systems

Distributing tasks to processors in distributed real time systems is an important step for obtaining high performance. Scheduling algorithms play a vital role in achieving better performance and high throughput in heterogeneous distributed real time systems. To make the best use of the computational power available, it is essential to assign the tasks to the processor whose characteristics are most appropriate for the execution of the tasks in a distributed processing system. This study develops two algorithms for clustering the heavily-communicating tasks to reduce the inter-tasks communication costs by using k-means and fuzzy c-means clustering techniques respectively. In order to minimize the system cost and response time, an algorithm is developed for the proper allocation of formed clusters to the most suitable processor. The present algorithms are collated with problems in literature. The proposed algorithms are formulated and applied to numerous numerical examples to demonstrate their effectiveness.

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

2016 ◽  
Vol 24 (2) ◽  
pp. 434-443 ◽  
Author(s):  
Shiann-Rong Kuang ◽  
Kun-Yi Wu ◽  
Ren-Yao Lu
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Vlsi Architecture ◽  
Modular Multiplication ◽  
Montgomery Modular Multiplication

Efficient Hardware Architecture for Kernel Fuzzy C-Means Algorithm

2013 ◽  
Vol 284-287 ◽  
pp. 3079-3086
Author(s):  
Chien Min Ou ◽  
Wen Jyi Hwang ◽  
Ssu Min Yang
Keyword(s):  
High Performance ◽  
Computational Cost ◽  
Vlsi Architecture ◽  
Kernel Functions ◽  
Hardware Accelerator ◽  
Fuzzy C Means ◽  
System On Programmable Chip ◽  
Membership Matrix ◽  
Low Computational Cost ◽  
Fuzzy C Means Algorithm

A novel VLSI architecture for kernel fuzzy c-means algorithm is presented in this paper. The architecture consists of efficient circuits for the computation of kernel functions, membership coefficients and cluster centers. In addition, the usual iterative operations for updating the membership matrix and cluster centers are merged into one single updating process to evade the large storage requirement. The circuit is used as a hardware accelerator of a softcore processor in a system-on-programmable chip for physical performance measurement. Experimental results show that the proposed solution is an effective alternative for cluster analysis with low computational cost and high performance.

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