FPGA Implementation of Power Efficient Floating Point Fused Multiply-Add Unit
2016 ◽
Vol 23
(7)
◽
pp. 1669-1681
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2014 ◽
Vol 1008-1009
◽
pp. 668-671
Keyword(s):
2016 ◽
Vol 2
(3)
◽
pp. 174
Keyword(s):
2017 ◽
Vol 28
(10)
◽
pp. 2823-2837
◽
Keyword(s):
Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA
2017 ◽
Vol 11
(4)
◽
pp. 149-158
◽