A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits

Author(s):  
Soumya Ganguly ◽  
Abhishek Mittal ◽  
Syed Ershad Ahmed ◽  
M.B. Srinivas
2021 ◽  
Author(s):  
Vikas Rao ◽  
Haden Ondricek ◽  
Priyank Kalla ◽  
Florian Enescu

2021 ◽  
pp. 2150011
Author(s):  
Grzegorz Rafał Dec

This paper presents and discusses the implementation of an LSTM cell on an FPGA with an activation function inspired by the CORDIC algorithm. The realization is performed using both IEEE754 standard and 32-bit integer numbers. The case with floating-point arithmetic is analyzed with and without DSP blocks provided by the Xilinx design suite. The alternative implementation including the integer arithmetic was optimized for a minimal number of clock cycles. Presented implementation uses xc6slx150t-2fgg900 and achieves high calculations accuracy for both cases.


Author(s):  
G. Navabharat Reddy ◽  
P. A. Harsha Vardhini ◽  
V. Prakasam ◽  
P. Sandeep

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