A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits
Keyword(s):
2016 ◽
Vol 23
(7)
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pp. 1669-1681
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Keyword(s):
2017 ◽
Vol 28
(10)
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pp. 2823-2837
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Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA
2017 ◽
Vol 11
(4)
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pp. 149-158
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2017 ◽
Vol 51
◽
pp. 366-385
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Keyword(s):