A low power sample and hold circuit for 16 bit 100 MS/s pipelined ADC
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2010 ◽
Vol 57
(3)
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pp. 163-167
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2017 ◽
Vol 11
(6)
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pp. 589-596
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2007 ◽
Vol 54
(4)
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pp. 1195-1200
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2019 ◽
Vol 66
(9)
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pp. 3352-3364
2004 ◽
Vol 51
(11)
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pp. 2123-2132
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