split capacitor
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Author(s):  
Izni Binti Mustafar ◽  
Naziha Binti Ahmad Azli ◽  
Norjulia Binti Mohamad Nordin

Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.


Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1016
Author(s):  
Riccardo Mandrioli ◽  
Manel Hammami ◽  
Aleksandr Viatkin ◽  
Riccardo Barbone ◽  
Davide Pontara ◽  
...  

The current switching ripple in a three-phase four-wire split-capacitor converter is analyzed in this paper for all the four ac output wires in relation to both balanced and unbalanced working conditions. Specifically, analytical formulations of the peak-to-peak and root mean square (RMS) current ripples are originally evaluated as a function of the modulation index, separately for the three phases and the neutral wire. Initially, the single-carrier sinusoidal pulse width modulation (PWM) technique is outlined, as it generally concerns a straightforward and effective modulation. With the aim of mitigating the current ripple in the neutral wire, the interleaved multiple-carrier PWM strategy is adopted, also avoiding any repercussion on the phase one. Numerical simulations and experimental tests were carried out to verify all the analytical developments.


2021 ◽  
Vol 68 (2) ◽  
pp. 1445-1453
Author(s):  
Kisu Kim ◽  
Honnyong Cha

Author(s):  
Riccardo Mandrioli ◽  
Aleksandr Viatkin ◽  
Manel Hammami ◽  
Mattia Ricco ◽  
Gabriele Grandi

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