scholarly journals Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores

1995 ◽  
Author(s):  
Adwin H. Timmer
Keyword(s):  
Code Generation ◽  
Instruction Scheduling

scholarly journals Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures

2013 ◽  
Vol 2013 ◽  
pp. 1-11 ◽  
Author(s):  
Haijing Tang ◽  
Xu Yang ◽  
Siye Wang ◽  
Yanjun Zhang
Keyword(s):  
Energy Consumption ◽  
Code Generation ◽  
Compiler Optimization ◽  
Instruction Scheduling ◽  
Optimization Techniques ◽  
Generation Process ◽  
Register File ◽  
Access Port ◽  
Common Trend ◽  
Cluster Data

Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explicit inter-cluster data move operations in traditional bus-connected clustered (BCC) VLIW architecture. However, the limit number of access ports to the global register file has become an issue which must be well addressed; otherwise the performance and energy consumption would be harmed. In this paper, we presented compiler optimization techniques for an RFCC VLIW architecture called Lily, which is designed for encryption systems. These techniques aim at optimizing performance and energy consumption for Lily architecture, through appropriate manipulation of the code generation process to maintain a better management of the accesses to the global register file. All the techniques have been implemented and evaluated. The result shows that our techniques can significantly reduce the penalty of performance and energy consumption due to access port limitation of global register file.

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory

Privacy Concern Code Generation Using Crypto Neural Scheme

2019 ◽  
Vol 7 (5) ◽  
pp. 824-828
Author(s):  
Anaswara Venunadh ◽  
Shruthi N ◽  
Mannar Mannan
Keyword(s):  
Code Generation ◽  
Privacy Concern

Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

2009 ◽  
Vol 31 (1) ◽  
pp. 127-132
Author(s):  
Zhi-Xiong ZHOU ◽  
Hu HE ◽  
Xu YANG ◽  
Yan-Jun ZHANG ◽  
Yi-He SUN
Keyword(s):  
Scheduling Algorithm ◽  
Instruction Scheduling ◽  
Register File

Realization of NAND FLASH Control Glueless Interface Circuit

2014 ◽  
Vol 1008-1009 ◽  
pp. 659-662
Author(s):  
Hai Ke Liu ◽  
Shun Wang ◽  
Xin Gna Kang ◽  
Jin Liang Wang
Keyword(s):  
Error Correction ◽  
Code Generation ◽  
Nand Flash ◽  
Timing Control ◽  
Interface Circuit ◽  
Advantages And Disadvantages ◽  
Operation Sequence ◽  
Control Interface

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

An experiment in table driven code generation

1982 ◽  
Vol 17 (6) ◽  
pp. 32-43 ◽  
Author(s):  
Susan L. Graham ◽  
Robert R. Henry ◽  
Robert A. Schulman
Keyword(s):  
Code Generation
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