Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling

Author(s):  
Mohsen Hassanpourghadi ◽  
Shiyu Su ◽  
Rezwan A Rasul ◽  
Juzheng Liu ◽  
Qiaochu Zhang ◽  
...  
2019 ◽  
Vol 213 ◽  
pp. 487-510 ◽  
Author(s):  
Melika Payvand ◽  
Manu V. Nair ◽  
Lorenz K. Müller ◽  
Giacomo Indiveri

In this paper, we present a spiking neural network architecture that supports the use of non-ideal memristive devices as synaptic elements and propose mixed-signal analog-digital interfacing circuits to mitigate/exploit such non-idealities for neuromorphic computation.


2019 ◽  
Vol 10 (1) ◽  
pp. 125-128 ◽  
Author(s):  
Yuxi Liu

Abstract This paper presents an innovative cognitive neural network method application in digital image recognition. The following conclusion can be drawn. Each point of the graph is transformed, and the original color of the transformed new coordinates is given to the point. If after all the points have transformed, if there is a point and no point has converted to this point, the point is not given a color. Then this point will form a hole or a stripe, and the color is the color of the point initialization. The innovative method can effectively separate the digital image recognition signal from the mixed signal and maintain the waveform of the source signal with high accuracy, thus laying the foundation for the next step of recognition.


1998 ◽  
Vol 08 (05n06) ◽  
pp. 589-604
Author(s):  
HORMOZ DJAHANSHAHI ◽  
MAJID AHMADI ◽  
GRAHAM A. JULLIEN ◽  
WILLIAM C. MILLER

This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular Arrays of a nonlinearly-loaded multiplier block form the core of multi-layer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Salient features of the present architecture, such as modularity and reduced interconnection problems and areas are highlighted and circuit design and improvements are presented for its universal building block. Other design issues such as supply voltage and power reduction and pin limitations are discussed together with experimental results.


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