scholarly journals High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

2012 ◽  
Author(s):  
C. Bolchini ◽  
A. Miele ◽  
C. Sandionigi ◽  
M. Ottavi ◽  
S. Pontarelli ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
High Reliability ◽  
Digital Systems ◽  
Design Methodologies

Fault-tolerant digital systems development using triple modular redundancy

2017 ◽  
Vol 8 (1) ◽  
pp. 3-7 ◽  
Author(s):  
R. Şinca ◽  
CS. Szász
Keyword(s):  
Large Scale ◽  
Fault Tolerant ◽  
High Reliability ◽  
Systems Development ◽  
Digital Systems ◽  
Design Solution ◽  
Triple Modular Redundancy ◽  
Wide Range ◽  
Hardware Architectures ◽  
Modular Redundancy

The paper presents a fault-tolerant digital system design and development strategy for high reliability hardware architectures implementation. Starting from the general consideration that digital hardware systems play a key role in a large scale of control systems implementation, a triple modular redundancy (TMR) solution it is proposed for development. For this reason, the well-known 1 bit majority voter configuration has been extended and generalized to the full control bus of a digital control system. Computer simulations show that the proposed hardware solution fulfills in all the theoretical expectations and it can be used for experimental tests and implementation. The presented design solution and conclusions are well suited to generalization for a wide range of fault-tolerant digital systems development ranging from reliable and safety servo control applications up to high reliability parallel and distributed computing hardware architectures.

scholarly journals Issues in Design and Development of Reliable Configurable Distributed Checkout and Launch System for Mission Critical Aero-Space Flight Vehicles

2020 ◽  
Vol 9 (4S2) ◽  
pp. 77-81
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Critical Parameters ◽  
Health Checks ◽  
Flight Vehicles ◽  
Mission Critical ◽  
Criticality Analysis

Role of Configurable Distributed Checkout and Launch System (CDCLS) is pivotal in carrying out quick health checks and launching of Aerospace Flight Vehicles. Configurable Distributed Architecture provides flexibility for connecting nodes and scaling Distributed System. Different configurations can be derived from the Master Configuration. Since, Ultra high reliability and infallible performance of the CDCLS is of paramount importance, Safety criticality and Mission criticality analysis needs to be carried out for determination of mission critical parameters. These critical parameters need to be addressed by required fault tolerant architecture, which can be implemented in Hardware and Software for achieving system reliability objective (Say, 0.99).

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

Improved Approach for Maximizing Reliability in Fault Tolerant Networks

2013 ◽  
Vol 17 (1) ◽  
pp. 27-41 ◽  
Author(s):  
Baijnath Kaushik ◽  
◽  
Navdeep Kaur ◽  
Amit Kumar Kohli ◽  
◽  
...  
Keyword(s):  
Neural Network ◽  
Network Design ◽  
Fault Tolerant ◽  
High Reliability ◽  
Computational Cost ◽  
Computational Effort ◽  
Alternative Methods ◽  
Optimal Network Design ◽  
Optimal Network ◽  
Simulation Based

The objective of this paper is to present a novelmethod for achievingmaximumreliability in fault-tolerant optimal network design when networks have variable size. Reliability calculation is a most important and critical component when fault-tolerant optimal network design is required. A network must be supplied with certain parameters that guarantee proper functionality and maintainability in worse-case situations. Many alternative methods for measuring reliability have been stated in the literature for optimal network design. Most of these methods, mentioned in the literature for evaluating reliability, may be analytical and simulation-based. These methods provide significant ways for computing reliability when a network has a limited size. Significant computational effort is also required for growing variable-sized networks. A novel neural network method is therefore presented to achieve significant high reliability in fault-tolerant optimal network design in highly growing variable networks. This paper compares simulation-based analytical methods with improved learning rate gradient descent-based neural network methods. Results show that improved optimal network design with maximum reliability is achievable by a novel neural network at a manageable computational cost.

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