Fault Tolerant Five-Level Active NPC Inverter for High-Reliability Photovoltaic Applications

2021 ◽  
Author(s):  
Majid T. Fard ◽  
JiangBiao He
Keyword(s):  
Fault Tolerant ◽  
High Reliability ◽  
Photovoltaic Applications

scholarly journals Issues in Design and Development of Reliable Configurable Distributed Checkout and Launch System for Mission Critical Aero-Space Flight Vehicles

2020 ◽  
Vol 9 (4S2) ◽  
pp. 77-81
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Critical Parameters ◽  
Health Checks ◽  
Flight Vehicles ◽  
Mission Critical ◽  
Criticality Analysis

Role of Configurable Distributed Checkout and Launch System (CDCLS) is pivotal in carrying out quick health checks and launching of Aerospace Flight Vehicles. Configurable Distributed Architecture provides flexibility for connecting nodes and scaling Distributed System. Different configurations can be derived from the Master Configuration. Since, Ultra high reliability and infallible performance of the CDCLS is of paramount importance, Safety criticality and Mission criticality analysis needs to be carried out for determination of mission critical parameters. These critical parameters need to be addressed by required fault tolerant architecture, which can be implemented in Hardware and Software for achieving system reliability objective (Say, 0.99).

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

Improved Approach for Maximizing Reliability in Fault Tolerant Networks

2013 ◽  
Vol 17 (1) ◽  
pp. 27-41 ◽  
Author(s):  
Baijnath Kaushik ◽  
◽  
Navdeep Kaur ◽  
Amit Kumar Kohli ◽  
◽  
...  
Keyword(s):  
Neural Network ◽  
Network Design ◽  
Fault Tolerant ◽  
High Reliability ◽  
Computational Cost ◽  
Computational Effort ◽  
Alternative Methods ◽  
Optimal Network Design ◽  
Optimal Network ◽  
Simulation Based

The objective of this paper is to present a novelmethod for achievingmaximumreliability in fault-tolerant optimal network design when networks have variable size. Reliability calculation is a most important and critical component when fault-tolerant optimal network design is required. A network must be supplied with certain parameters that guarantee proper functionality and maintainability in worse-case situations. Many alternative methods for measuring reliability have been stated in the literature for optimal network design. Most of these methods, mentioned in the literature for evaluating reliability, may be analytical and simulation-based. These methods provide significant ways for computing reliability when a network has a limited size. Significant computational effort is also required for growing variable-sized networks. A novel neural network method is therefore presented to achieve significant high reliability in fault-tolerant optimal network design in highly growing variable networks. This paper compares simulation-based analytical methods with improved learning rate gradient descent-based neural network methods. Results show that improved optimal network design with maximum reliability is achievable by a novel neural network at a manageable computational cost.

Operational fault-tolerant microcomputer for very high reliability

1983 ◽  
Vol 130 (3) ◽  
pp. 90 ◽  
Author(s):  
Mashkuri Yaacob ◽  
M.G. Hartley ◽  
P.G. Depledge
Keyword(s):  
Fault Tolerant ◽  
High Reliability ◽  
Very High

FAULT-TOLERANT PARALLEL ALGORITHMS FOR ADAPTIVE MATCHED-FIELD PROCESSING ON DISTRIBUTED ARRAY SYSTEMS

2005 ◽  
Vol 13 (04) ◽  
pp. 667-687 ◽  
Author(s):  
KILSEOK CHO ◽  
ALAN D. GEORGE ◽  
RAJ SUBRAMANIYAN
Keyword(s):  
Parallel Algorithms ◽  
Real Time ◽  
Fault Tolerant ◽  
High Reliability ◽  
Computation Time ◽  
Coarse Grained ◽  
Beam Power ◽  
Matched Field Processing ◽  
Distributed Array ◽  
Sonar Systems

Continuous innovations in adaptive matched-field processing (MFP) algorithms have presented significant increases in computational complexity and resource requirements that make development and use of advanced parallel processing techniques imperative. In real-time sonar systems operating in severe underwater environments, there is a high likelihood of some part of systems exhibiting defective behavior, resulting in loss of critical network, processor, and sensor elements, and degradation in beam power pattern. Such real-time sonar systems require high reliability to overcome these challenging problems. In this paper, efficient fault-tolerant parallel algorithms based on coarse-grained domain decomposition methods are developed in order to meet real-time and reliability requirements on distributed array systems in the presence of processor and sensor element failures. The performance of the fault-tolerant parallel algorithms is experimentally analyzed in terms of beamforming performance, computation time, speedup, and parallel efficiency on a distributed testbed. The performance results demonstrate that these fault-tolerant parallel algorithms can provide real-time, scalable, lightweight, and fault-tolerant implementations for adaptive MFP algorithms on distributed array systems.

Super-High Reliability Fault-Tolerant System NURECS-3000

1986 ◽  
Vol IE-33 (2) ◽  
pp. 148-151 ◽  
Author(s):  
Kazuo Asami ◽  
Katsuya Yanai ◽  
Tetsuo Ito
Keyword(s):  
Fault Tolerant ◽  
High Reliability ◽  
Fault Tolerant System
Sign in / Sign up

Export Citation Format

Share Document