Maintainability of electronic instruments for meteorological applications

The concept of Maintainability (M) of electronic instruments. though of recent origin, has Important application for meteorological equipments, which have special requirements. M is defined quantitatively in terms of mean time to repair and is Influenced by the failure behaviour of an equipment. An equipment goes through teething trouble, useful and terminal phase. Much of maintainability can be incorporated during design and production phase. This reduces the effective overall cost of the equipment during its life time. Special maintenance support system is necessary for meteorological Instruments. Some recent tools for trouble shooting in digital systems have been discussed.

A Thermally Stable Quasi-CMOS Bipolar Logic

Logic gates made of pairs of NPN and PNP bipolar transistors, similar to CMOS logic gates, have been proposed and patented long ago but did not find any practical application until now. Other bipolar technologies (TTL, TTL-S, ECL), once the technologies of choice for digital systems, were abandoned and superseded by CMOS. In this paper it is shown that now, when truly complementary pairs of bipolar transistors can be made, properly biased bipolar gates similar to CMOS gates are feasible, can be thermally stable and find practical applications.

Immersed, yet distant: Notes for an aesthetic theory of immersive travel films

The purpose of this article is to highlight a few stylistic and aesthetic principles, common to the genre of the travel film (both documentary and fictional), as employed by immersive media and devices from the twentieth century – such as the Hale’s Tours of the World, Todd-AO, and Cinerama – up to today’s digital systems like Virtual Reality and 4D Cinema. I will discuss how the different experiences of simulated travels, proffered by those media, are all related to a broader aesthetic tendency in creating what I label as enveloping tactile images. Such images are programmed to surround the viewer from every side, thus increasing their spectacular dimension, but at the same time they strive to temper and weaken the haptic solicitations aroused in the viewer by the immersive apparatus itself. In this sense I propose that the spectator of immersive travelogue films is ‘immersed, yet distant’: she is tangled in the illusion of traversing an enveloping visual space, but the position she occupies is nonetheless a metaphysical one, not different from that of Renaissance perspective, because even if she can see everything, the possibility to interact with the images is denied, in order to preserve the realistic illusion. By analysing the stylistic techniques employed to foster the viewer’s condition of non-interactive immersion in the enveloping world presented by the medium, I will consequently address the topic of the conflict that such immersive aesthetics establish with traditional forms of audiovisual storytelling.

Development of the Architecture of the System of High-Load Testing

Testing system performance and its importance at the same time is difficult to overestimate or underestimate. It would be much more correct to talk about the timeliness of this activity. Virtually any digital sys- tem built on modern approaches and technologies can work without any critical problems with its own performance. At the same time, for any system, especially when it becomes popular, it is very likely that there will be a time when it will not be able to cope with the ever-increasing load and become unstable. However, most companies that develop and maintain their own digital solutions – from websites to any other digital systems – often focus primarily on the functionality of the system and its compliance, rather than on the performance of the system as a whole. Such intentions are quite natural, because the system must properly perform the functions expected of it. When companies start to face performance problems, they try not to optimize the software as soon as possible, but to add more capacity – vertical and horizontal scaling. This strategy works, but it has limitations. After all, the addition of additional resources cannot be endless and sooner or later rests either on the architecture of the system, or in the capabilities of the company itself, and so on.Therefore it is recommended to carry out stress testing in advance, plan time and resources to have enough time to correct errors, and generally understand the boundaries of the system. At the same time, in order to organize full-fledged stress testing, trained specialists, tools and infrastructure are needed, especially when we are talking about heavy workload.As part of this work, an analysis of various tools for the implementation of stress testing and performance testing, scaling of such tests and centralized reporting of metrics. As a result, approaches and principles for the construction of a modern architecture for the implementation of the load testing subsystem in the continuous supply of code were proposed.

Power optimization of binary division based on FPGA

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.

Advancing Sociotechnical-Pedagogical Heuristics for the Usability Evaluation of Online Courses for Adult Learners

Online courses often include interface designs that do not support a positive learner experience. Literature shows a variety of heuristics to detect issues of online courses. While heuristic-based inspection of usability is a dominant method for evaluating digital systems, these methods cannot be easily transferred to online courses. To close this gap, we identified an initial set of social, technical, and pedagogical related items (STP) heuristics based on literature. Next, we analyzed this set using empirical data from two online courses. In total, we analyzed 195 problems with the goal to substantiate a final set of 14 STP heuristics. This new set allows for efficiently evaluating online courses by supporting evaluators and instructional designers in uncovering the most crucial issues and improving the learner experience. Finally, based on this work, we discuss a definition of learner experience for the emerging field of learner experience design and research.

Optical digital-to-analog converter for N-digit logic-based processing circuits

The possibility of synthesis of ultra-fast universal optical digital-to-analog converter (DAC) providing conversion of digital information into analog information in giga- and terahertz ranges, including in digital systems based on N-digit logic, is considered. The functional diagram of the optical DAC containing technologically well-developed optical elements is given, the principle of operation is described in detail. The possibility of implementing this DAC with the speed potentially possible for optical data processing circuits is shown.