Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing

2017 ◽  
Author(s):  
Charles Effiong ◽  
Gilles Sassatelli ◽  
Abdoulaye Gamatie
Keyword(s):  
Efficient Implementation ◽  
Power Efficient ◽  
Buffer Sharing

Power Efficient Implementation of Least Mean Square Algorithm Based FIR Filter Design Using FPGA

2014 ◽  
Vol 2 (1) ◽  
pp. 14-21
Author(s):  
M. Devipriya ◽  
◽  
V. Saravanan ◽  
N. Santhiyakumari ◽  
◽  
...  
Keyword(s):  
Filter Design ◽  
Fir Filter ◽  
Efficient Implementation ◽  
Mean Square ◽  
Least Mean Square ◽  
Power Efficient ◽  
Least Mean Square Algorithm ◽  
Fir Filter Design

A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications

2021 ◽  
Author(s):  
Binh Kieu-Do-Nguyen ◽  
Trong-Thuc Hoang ◽  
Cong-Kha Pham ◽  
Cuong Pham-Quoc
Keyword(s):  
Hash Function ◽  
Efficient Implementation ◽  
Power Efficient ◽  
Embedded Applications

SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA

2015 ◽  
Vol 9 (7) ◽  
pp. 267-274 ◽  
Author(s):  
Bishwajeet Pandey ◽  
Vandana Thind ◽  
Simran Kaur Sandhu ◽  
Tamanna Walia ◽  
Sumit Sharma
Keyword(s):  
Efficient Implementation ◽  
Power Efficient ◽  
Security Algorithm

Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique

2008 ◽  
Vol 47 (4) ◽  
pp. 2807-2811 ◽  
Author(s):  
Liem T. Nguyen ◽  
Kiyoto Ito ◽  
Tadashi Shibata
Keyword(s):  
Time Domain ◽  
Rank Order ◽  
Efficient Implementation ◽  
Power Efficient ◽  
Digital Computation ◽  
Computation Technique
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