Design and Verification of 16 bit RISC Processor Using Vedic Mathematics

2021 International Conference on Emerging Smart Computing and Informatics (ESCI) ◽

10.1109/esci50559.2021.9396965 ◽

2021 ◽

Author(s):

Ankita Yadav ◽

Varsha Bendre

Keyword(s):

Vedic Mathematics ◽

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DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.6.4.14864 ◽

2018 ◽

Vol 6 (4) ◽

pp. 38

Author(s):

S. M. BHAGAT ◽

S. U. BHANDARI ◽

◽

Keyword(s):

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High speed convolution and deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)

2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) ◽

10.1109/ecticon.2014.6839756 ◽

2014 ◽

Author(s):

Surabhi Jain ◽

Sandeep Saini

Keyword(s):

Vedic Mathematics ◽

Deconvolution Algorithm

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FPGA prototyping of a RISC processor core for embedded applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924027 ◽

2001 ◽

Vol 9 (2) ◽

pp. 241-250 ◽

Author(s):

M. Gschwind ◽

V. Salapura ◽

D. Maurer

Keyword(s):

Processor Core ◽

Risc Processor ◽

Embedded Applications

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Design of High Performance ALU Using Vedic Mathematics

Journal of Physics Conference Series ◽

10.1088/1742-6596/1964/6/062031 ◽

2021 ◽

Vol 1964 (6) ◽

pp. 062031

Author(s):

V Swathi ◽

Kavitha Panduga ◽

Gurrala Shiva Kumari

Keyword(s):

High Performance ◽

Vedic Mathematics

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Design of Efficient Dynamic Scheduling of RISC Processor Instructions

2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) ◽

10.1109/iemcon51383.2020.9284902 ◽

2020 ◽

Author(s):

Anudeep Bonasu ◽

Sushanth Reddy Karmunchi ◽

Nan Wang

Keyword(s):

Dynamic Scheduling ◽

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Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform

Sadhana ◽

10.1007/s12046-021-01605-4 ◽

2021 ◽

Vol 46 (2) ◽

Author(s):

Rhea Biji ◽

Vijay Savani

Keyword(s):

Performance Analysis ◽

Hardware Platform ◽

Vedic Mathematics ◽

Configurable Hardware

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Use of Vedic Mathematics to Speed-up Basic Mathematical Operations in Android Based Calculator

2019 International Conference on Intelligent Sustainable Systems (ICISS) ◽

10.1109/iss1.2019.8907961 ◽

2019 ◽

Author(s):

Lakshmi Mandal ◽

Kousik Dasgupta

Keyword(s):

Vedic Mathematics ◽

Speed Up ◽

Mathematical Operations

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Efficient Color Space Conversion using Custom Instruction in a RISC Processor

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378204 ◽

2007 ◽

Author(s):

Muhammad Bilal ◽

Shahid Masud

Keyword(s):

Color Space ◽

Custom Instruction ◽

Color Space Conversion ◽

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The simulation of a RISC processor with N.MPC

Proceedings of the 1985 ACM annual conference on The range of computing : mid-80's perspective mid-80's perspective - ACM '85 ◽

10.1145/320435.320512 ◽

1985 ◽

Author(s):

Charles A. Baxley ◽

Frederick A. Zapka

Keyword(s):

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An automated development framework for a RISC processor with reconfigurable instruction set extensions

Proceedings 20th IEEE International Parallel & Distributed Processing Symposium ◽

10.1109/ipdps.2006.1639476 ◽

2006 ◽

Author(s):

N. Vassiliadis ◽

G. Theodoridis ◽

S. Nikolaidis

Keyword(s):

Instruction Set ◽

Development Framework ◽

Risc Processor ◽

Instruction Set Extensions

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