Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories

Author(s):  
Yuriko Ishitobi ◽  
Tohru Ishihara ◽  
Hiroto Yasuura
Author(s):  
F.R. Cordeiro ◽  
A.G. Silva-Filho ◽  
C.C. Araujo ◽  
M. Gomes ◽  
E.N.S. Barros ◽  
...  

2021 ◽  
Author(s):  
Mohammad Hasan Ahmadilivani ◽  
Mohammad Moeini Jahromi ◽  
Mostafa E. Salehi ◽  
Mona Kargar

<p>The reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in the design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different programs leads to incompatible vulnerability patterns in them. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).</p>


2021 ◽  
Author(s):  
Mohammad Hasan Ahmadilivani ◽  
Mohammad Moeini Jahromi ◽  
Mostafa E. Salehi ◽  
Mona Kargar

Reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in design of a reliable system especially for safety-critical applications.<br>It has been shown that using the same cache sizes for different applications leads to incompatible vulnerability patterns in applications. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for<br>different programs would need a huge design space exploration.<br>In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average). <br>


2021 ◽  
Author(s):  
Mohammad Hasan Ahmadilivani ◽  
Mohammad Moeini Jahromi ◽  
Mostafa E. Salehi ◽  
Mona Kargar

Reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in design of a reliable system especially for safety-critical applications.<br>It has been shown that using the same cache sizes for different applications leads to incompatible vulnerability patterns in applications. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for<br>different programs would need a huge design space exploration.<br>In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average). <br>


2008 ◽  
Vol 60 (2) ◽  
pp. 211-224 ◽  
Author(s):  
Yuriko Ishitobi ◽  
Tohru Ishihara ◽  
Hiroto Yasuura

2021 ◽  
Author(s):  
Mohammad Hasan Ahmadilivani ◽  
Mohammad Moeini Jahromi ◽  
Mostafa E. Salehi ◽  
Mona Kargar

<p>The reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in the design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different programs leads to incompatible vulnerability patterns in them. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).</p>


Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 337 ◽  
Author(s):  
Daniele Jahier Pagliari ◽  
Francesco Daghero ◽  
Massimo Poncino

Sequence-to-sequence deep neural networks have become the state of the art for a variety of machine learning applications, ranging from neural machine translation (NMT) to speech recognition. Many mobile and Internet of Things (IoT) applications would benefit from the ability of performing sequence-to-sequence inference directly in embedded devices, thereby reducing the amount of raw data transmitted to the cloud, and obtaining benefits in terms of response latency, energy consumption and security. However, due to the high computational complexity of these models, specific optimization techniques are needed to achieve acceptable performance and energy consumption on single-core embedded processors. In this paper, we present a new optimization technique called dynamic beam search, in which the inference complexity is tuned to the difficulty of the processed input sequence at runtime. Results based on measurements on a real embedded device, and on three state-of-the-art deep learning models, show that our method is able to reduce the inference time and energy by up to 25% without loss of accuracy.


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