ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

Design Space ◽

Space Exploration ◽

Embedded Processors ◽

Reliable System ◽

Cache Memories ◽

Program Behavior ◽

Safety Critical ◽

Cache Size ◽

The reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in the design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different programs leads to incompatible vulnerability patterns in them. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).

ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

10.36227/techrxiv.14730219.v1 ◽

2021 ◽

Author(s):

Mohammad Hasan Ahmadilivani ◽

Mohammad Moeini Jahromi ◽

Mostafa E. Salehi ◽

Mona Kargar

Keyword(s):

Design Space ◽

Space Exploration ◽

Embedded Processors ◽

Reliable System ◽

Cache Memories ◽

Program Behavior ◽

Safety Critical ◽

Cache Size ◽

Reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different applications leads to incompatible vulnerability patterns in applications. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).

ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

10.36227/techrxiv.14730219 ◽

2021 ◽

Author(s):

Mohammad Hasan Ahmadilivani ◽

Mohammad Moeini Jahromi ◽

Mostafa E. Salehi ◽

Mona Kargar

Keyword(s):

Design Space ◽

Space Exploration ◽

Embedded Processors ◽

Reliable System ◽

Cache Memories ◽

Program Behavior ◽

Safety Critical ◽

Cache Size ◽

Reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different applications leads to incompatible vulnerability patterns in applications. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).

A rapid design space exploration approach for multi-objective optimization of DSP filter designs

10.32920/ryerson.14653857.v1 ◽

2021 ◽

Author(s):

Aakriti Tarun Sharma

Keyword(s):

Design Space ◽

Space Exploration ◽

Systems Design ◽

Design Solution ◽

Multi Objective Optimization ◽

Multi Objective ◽

Time Period ◽

And Performance ◽

High Level

The process of converting a behavioral specification of an application to its equivalent system architecture is referred to as High Level-Synthesis (HLS). A crucial stage in embedded systems design involves finding the trade off between resource utilization and performance. An exhaustive search would yield the required results, but would take a huge amount of time to arrive at the solution even for smaller designs. This would result in a high time complexity. We employ the use of Design Space Exploration (DSE) in order to reduce the complexity of the design space and to reach the desired results in less time. In reality, there are multiple constraints defined by the user that need to be satisfied simultaneously. Thus, the nature of the task at hand is referred to as Multi-Objective Optimization. In this thesis, the design process of DSP benchmarks was analyzed based on user defined constraints such as power and execution time. The analyzed outcome was compared with the existing approaches in DSE and an optimal design solution was derived in a shorter time period.

CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration

CMOS Processors and Memories ◽

10.1007/978-90-481-9216-8_4 ◽

2010 ◽

pp. 97-138 ◽

Cited By ~ 1

Author(s):

Dan Hammerstrom ◽

Mazad S. Zaveri

Keyword(s):

Bayesian Inference ◽

Design Space ◽

Space Exploration ◽

Hardware Design ◽

Inference Engine ◽

Mixed Signal ◽

Preliminary Design and Performance of Counter Rotating Turbines for Open Rotors: Part II — 0-D Methodology and Case Study for a 160 PAX Aircraft

Volume 1: Aircraft Engine; Fans and Blowers; Marine ◽

10.1115/gt2016-57921 ◽

2016 ◽

Author(s):

Pablo Bellocq ◽

Inaki Garmendia ◽

Jordane Legrand ◽

Vishal Sethi

Keyword(s):

Design Methodology ◽

Design Space ◽

Space Exploration ◽

Preliminary Design ◽

Regulatory Constraints ◽

Trade Offs ◽

And Performance ◽

The Impact

Direct Drive Open Rotors (DDORs) have the potential to significantly reduce fuel consumption and emissions relative to conventional turbofans. However, this engine architecture presents many design and operational challenges both at engine and aircraft level. At preliminary design stages, a broad design space exploration is required to identify potential optimum design regions and to understand the main trade offs of this novel engine architecture. These assessments may also aid the development process when compromises need to be performed as a consequence of design, operational or regulatory constraints. Design space exploration assessments are done with 0-D or 1-D models for computational purposes. These simplified 0-D and 1-D models have to capture the impact of the independent variation of the main design and control variables of the engine. Historically, it appears that for preliminary design studies of DDORs, Counter Rotating Turbines (CRTs) have been modelled as conventional turbines and therefore it was not possible to assess the impact of the variation of the number of stages (Nb) of the CRT and rotational speed of the propellers. Additionally, no preliminary design methodology for CRTs was found in the public domain. Part I of this two-part publication proposes a 1-D preliminary design methodology for DDOR CRTs which allows an independent definition of both parts of the CRT. A method for calculating the off-design performance of a known CRT design is also described. In Part II, a 0-D design point efficiency calculation for CRTs is proposed and verified with the 1-D methods. The 1-D and 0-D CRT models were used in an engine control and design space exploration case study of a DDOR with a 4.26m diameter an 10% clipped propeller for a 160 PAX aircraft. For this application: • the design and performance of a 20 stage CRT rotating at 860 rpm (both drums) obtained with the 1-D methods is presented. • differently from geared open rotors, negligible cruise fuel savings can be achieved by an advanced propeller control. • for rotational speeds between 750 and 880 rpm (relatively low speeds for reduced noise), 22 and 20 stages CRTs are required. • engine weight can be kept constant for different design rotational speeds by using the minimum required Nb. • for any target engine weight, TOC and cruise SFC are reduced by reducing the rotational speeds and increasing Nb (also favourable for reducing CRP noise). However additional CRT stages increase engine drag, mechanical complexity and cost.

Volume 3: Coal, Biomass, Hydrogen, and Alternative Fuels; Cycle Innovations; Electric Power; Industrial and Cogeneration; Organic Rankine Cycle Power Systems ◽

A Framework for Optimization of Hybrid Aircraft

10.1115/gt2019-91335 ◽

2019 ◽

Cited By ~ 2

Author(s):

Xin Zhao ◽

Smruti Sahoo ◽

Konstantinos Kyprianidis ◽

Sharmila Sumsurooah ◽

Giorgio Valente ◽

...

Keyword(s):

Conceptual Design ◽

Design Space ◽

Space Exploration ◽

Aircraft Structure ◽

Simulation And Optimization ◽

Trade Offs ◽

And Performance ◽

Full Design ◽

Aircraft Conceptual Design

Abstract To achieve the goals of substantial improvements in efficiency and emissions set by Flightpath 2050, fundamentally different concepts are required. As one of the most promising solutions, electrification of the aircraft primary propulsion is currently a prime focus of research and development. Unconventional propulsion sub-systems, mainly the electrical power system, associated thermal management system and transmission system, provide a variety of options for integration in the existing propulsion systems. Different combinations of the gas turbine and the unconventional propulsion sub-systems introduce different configurations and operation control strategies. The trade-off between the use of the two energy sources, jet fuel and electrical energy, is primarily a result of the trade-offs between efficiencies and sizing characteristics of these sub-systems. The aircraft structure and performance are the final carrier of these trade-offs. Hence, full design space exploration of various hybrid derivatives requires global investigation of the entire aircraft considering these key propulsion sub-systems and the aircraft structure and performance, as well as their interactions. This paper presents a recent contribution of the development for a physics-based simulation and optimization platform for hybrid electric aircraft conceptual design. Modeling of each subsystem and the aircraft structure are described as well as the aircraft performance modeling and integration technique. With a focus on the key propulsion sub-systems, aircraft structure and performance that interfaces with existing conceptual design frameworks, this platform aims at full design space exploration of various hybrid concepts at a low TRL level.

A rapid design space exploration approach for multi-objective optimization of DSP filter designs

10.32920/ryerson.14653857 ◽

2021 ◽

Author(s):

Aakriti Tarun Sharma

Keyword(s):

Design Space ◽

Space Exploration ◽

Systems Design ◽

Design Solution ◽

Multi Objective Optimization ◽

Multi Objective ◽

Time Period ◽

And Performance ◽

High Level

The process of converting a behavioral specification of an application to its equivalent system architecture is referred to as High Level-Synthesis (HLS). A crucial stage in embedded systems design involves finding the trade off between resource utilization and performance. An exhaustive search would yield the required results, but would take a huge amount of time to arrive at the solution even for smaller designs. This would result in a high time complexity. We employ the use of Design Space Exploration (DSE) in order to reduce the complexity of the design space and to reach the desired results in less time. In reality, there are multiple constraints defined by the user that need to be satisfied simultaneously. Thus, the nature of the task at hand is referred to as Multi-Objective Optimization. In this thesis, the design process of DSP benchmarks was analyzed based on user defined constraints such as power and execution time. The analyzed outcome was compared with the existing approaches in DSE and an optimal design solution was derived in a shorter time period.