ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

<p>The reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in the design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different programs leads to incompatible vulnerability patterns in them. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).</p>

ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

<p>The reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in the design of a reliable system especially for safety-critical applications. It has been shown that using the same cache sizes for different programs leads to incompatible vulnerability patterns in them. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for different programs would need a huge design space exploration. In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average).</p>

ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

Reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in design of a reliable system especially for safety-critical applications.<br>It has been shown that using the same cache sizes for different applications leads to incompatible vulnerability patterns in applications. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for<br>different programs would need a huge design space exploration.<br>In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average). <br>

ECS an Endeavor Towards Providing Similar Cache Reliability Behavior in Different Programs

Reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability is particularly expressed within the cache memories which are the largest part of new system on chips. Cache memories are the most vulnerable parts of the embedded systems and can affect the reliability drastically especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in design of a reliable system especially for safety-critical applications.<br>It has been shown that using the same cache sizes for different applications leads to incompatible vulnerability patterns in applications. According to the literature, most of the related researches, have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. Traditional attempts for finding an appropriate cache size for<br>different programs would need a huge design space exploration.<br>In this work, we have introduced a criterion for determining the Effective Cache Size (ECS) for embedded processors which considers the inherent programs’ reliability and performance properties. According to the results, using the ECS for the representative benchmark applications, the reliability would be increased 43x on average with acceptable performance degradations (21% on average). <br>

Flexible use of memory by food-caching birds in a laboratory behavioral paradigm

SummaryMemory is used by animals to influence navigational decisions, and neural activity in memory-related brain regions correlates to spatial variables. However, navigation is a rich behavior that contains a mix of memory-guided and memory-independent strategies. Disentangling the contribution of these strategies to navigation is therefore critical for understanding how memory influences behavioral output. To address this issue, we studied the natural spatial behavior of the chickadee, a food-caching bird. These birds hide food items at concealed, scattered locations and retrieve their caches later in time. We designed an apparatus that allows chickadees to cache and retrieve food while navigating in a laboratory arena. This apparatus enabled detailed, automated, and high-throughput tracking of key behavioral variables – including caches, retrievals, and investigations of cache sites. We built probabilistic models to fit these behavioral data using a combination of various mnemonic and non-mnemonic factors. We find that chickadees use some navigational strategies that are independent of cache memories, including opportunistic foraging and spatial biases. They combine these strategies with spatially precise and long-lasting memories of which sites contain caches and which sites they have previously checked and found to be empty. These memories are used in a context-dependent manner. During caching, chickadees avoid sites that already contain food. During retrieval, they are instead attracted to such occupied sites. These results show that a single memory can be used flexibly by a chickadee to achieve at least two unrelated behavioral goals. Our apparatus enables studying this flexibility in a tractable spatial paradigm.

A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.