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A technology mapping algorithm for PAL-based devices using multi-output function graphs
Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future
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10.1109/eurmic.2000.874627
◽
2002
◽
Cited By ~ 6
Author(s):
D. Kania
Keyword(s):
Technology Mapping
◽
Output Function
◽
Mapping Algorithm
Download Full-text
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Cited By
References
A new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs
1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
◽
10.1109/iscas.1996.542151
◽
2002
◽
Author(s):
K.N. Chen
◽
T.S. Wang
◽
Y.T. Lai
Keyword(s):
Technology Mapping
◽
Mapping Algorithm
◽
New Strategy
Download Full-text
MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays
18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.
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10.1109/ipdps.2004.1303140
◽
2004
◽
Author(s):
A.M. Kumar
◽
B. Jayaram
◽
R. Manimegalai
◽
V. Kamakoti
Keyword(s):
Technology Mapping
◽
Embedded Memory
◽
Mapping Algorithm
◽
Memory Arrays
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A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
◽
10.1109/iccad45719.2019.8942053
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2019
◽
Cited By ~ 2
Author(s):
Ghasem Pasandi
◽
Massoud Pedram
Keyword(s):
Dynamic Programming
◽
Technology Mapping
◽
Mapping Algorithm
◽
Area Minimization
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An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on physical design - ISPD '05
◽
10.1145/1055137.1055166
◽
2005
◽
Cited By ~ 8
Author(s):
Rupesh S. Shelar
◽
Prashant Saxena
◽
Xinning Wang
◽
Sachin S. Sapatnekar
Keyword(s):
Technology Mapping
◽
Efficient Technology
◽
Mapping Algorithm
◽
Delay Constraints
◽
Routing Congestion
Download Full-text
A new retiming-based technology mapping algorithm for LUT-based FPGAs
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays - FPGA '98
◽
10.1145/275107.275118
◽
1998
◽
Cited By ~ 40
Author(s):
Peichen Pan
◽
Chih-Chang Lin
Keyword(s):
Technology Mapping
◽
Mapping Algorithm
Download Full-text
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
IEEE/ACM International Conference on Computer-Aided Design
◽
10.1109/iccad.1992.279398
◽
1992
◽
Cited By ~ 58
Author(s):
Cong
◽
Ding
Keyword(s):
Lookup Table
◽
Technology Mapping
◽
Mapping Algorithm
◽
Delay Optimization
◽
Optimal Technology
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Technology mapping algorithm for heterogeneous field programmable gate arrays
IEE Proceedings - Computers and Digital Techniques
◽
10.1049/ip-cdt:20020748
◽
2002
◽
Vol 149
(6)
◽
pp. 249
◽
Cited By ~ 2
Author(s):
Y.-T. Lai
◽
C.-C. Kao
Keyword(s):
Field Programmable Gate Arrays
◽
Technology Mapping
◽
Mapping Algorithm
◽
Gate Arrays
◽
Field Programmable
◽
Programmable Gate Arrays
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Technology mapping algorithm targeting routing congestion under delay constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2006.870078
◽
2006
◽
Vol 25
(4)
◽
pp. 625-636
◽
Cited By ~ 4
Author(s):
R.S. Shelar
◽
P. Saxena
◽
S.S. Sapatnekar
Keyword(s):
Technology Mapping
◽
Mapping Algorithm
◽
Delay Constraints
◽
Routing Congestion
Download Full-text
A technology mapping algorithm for heterogeneous FPGAs
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
◽
10.1109/aspdac.2003.1195019
◽
2003
◽
Author(s):
Chi-Chou Kao
◽
Yen-Tai Lai
Keyword(s):
Technology Mapping
◽
Mapping Algorithm
Download Full-text
FMAP: a technology mapping algorithm for FPGA with MUX-LUT mixed architecture
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03
◽
10.1109/icasic.2003.1277334
◽
2003
◽
Author(s):
Wen Yujie
◽
Tong Jiarong
◽
Chiang
Keyword(s):
Technology Mapping
◽
Mapping Algorithm
Download Full-text
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