Technology mapping algorithm for heterogeneous field programmable gate arrays

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20020748 ◽

2002 ◽

Vol 149 (6) ◽

pp. 249 ◽

Author(s):

Y.-T. Lai ◽

C.-C. Kao

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Mapping Algorithm ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Maple: A Simultaneous Technology Mapping, Placement, And Global Routing Algorithm For Field-programmable Gate Arrays

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629759 ◽

2005 ◽

Author(s):

N. Togawa ◽

M. Sato ◽

T. Ohtsuki

Keyword(s):

Routing Algorithm ◽

Field Programmable Gate Arrays ◽

Global Routing ◽

Technology Mapping ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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General technology mapping for field-programmable gate arrays based on lookup tables

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/504914.504915 ◽

2002 ◽

Vol 7 (1) ◽

pp. 1-32

Author(s):

Amit Chowdhary ◽

John P. Hayes

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Gate Arrays ◽

Lookup Tables ◽

Field Programmable ◽

Programmable Gate Arrays ◽

General Technology

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Technology mapping and circuit depth optimization for field programmable gate arrays

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93 ◽

10.1109/cicc.1993.590373 ◽

2002 ◽

Author(s):

Shih-Chieh Chang ◽

M. Marek-Sadowska

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

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Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

Microprocessors and Microsystems ◽

10.1016/j.micpro.2006.04.002 ◽

2006 ◽

Vol 30 (7) ◽

pp. 445-456

Author(s):

Joshua M. Lucas ◽

Raymond Hoare ◽

Ivan S. Kourtev ◽

Alex K. Jones

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Content Addressable Memory ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Application of fuzzy logic for technology mapping of field-programmable gate arrays (FPGAs)

10.1117/12.243259 ◽

1996 ◽

Author(s):

Jun-Yong Lee ◽

Eugene B. Shragowitz

Keyword(s):

Fuzzy Logic ◽

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Chortle: a technology mapping program for lookup table-based field programmable gate arrays

27th ACM/IEEE Design Automation Conference ◽

10.1109/dac.1990.114927 ◽

2002 ◽

Author(s):

R.J. Francis ◽

J. Rose ◽

K. Chung

Keyword(s):

Field Programmable Gate Arrays ◽

Lookup Table ◽

Technology Mapping ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Mapping Program

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Area-optimal technology mapping for field-programmable gate arrays based on lookup tables

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.850893 ◽

2005 ◽

Vol 24 (7) ◽

pp. 999-1013 ◽

Author(s):

A. Chowdhary ◽

J.P. Hayes

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Gate Arrays ◽

Lookup Tables ◽

Field Programmable ◽

Optimal Technology ◽

Programmable Gate Arrays

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Technology mapping for field-programmable gate arrays using integer programming

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480139 ◽

2002 ◽

Author(s):

A. Chowdhary ◽

J.P. Hayes

Keyword(s):

Integer Programming ◽

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines ◽

10.1109/fccm.2006.68 ◽

2006 ◽

Author(s):

A.K. Jones ◽

I.S. Kourtev ◽

R. Hoare ◽

J.M. Lucas ◽

A.K. Jones ◽

...

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Content Addressable Memory ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

2020 28th European Signal Processing Conference (EUSIPCO) ◽

10.23919/eusipco47968.2020.9287739 ◽

2021 ◽

Author(s):

Niccolo Nicodemo ◽

Gaurav Naithani ◽

Konstantinos Drossos ◽

Tuomas Virtanen ◽

Roberto Saletti

Keyword(s):

Neural Networks ◽

Deep Neural Networks ◽

Field Programmable Gate Arrays ◽

Memory Requirement ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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